儲存庫 vbox 的更動 62357

時間撮記:

2016-7-20 下午01:03:13 (8 年 以前)

作者:

vboxsync

訊息:

VMM/GIM/HyperV: SynIC: APIC-assist page bits.

位置:

trunk/src/VBox/VMM

檔案:

• VMMAll/GIMAllHv.cpp (修改) (3 筆差異)
• VMMR3/GIMHv.cpp (修改) (1 筆差異)
• include/GIMHvInternal.h (修改) (1 筆差異)

trunk/src/VBox/VMM/VMMAll/GIMAllHv.cpp

@@ -678 +678 @@
             return VINF_CPUM_R3_MSR_WRITE;
 #else  /* IN_RING3 */
-            /* First, update all but the TSC-page enable bit. */
+            /* First, update all but the TSC page enable bit. */
             pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
 
-            /* Is the guest disabling the TSC-page? */
+            /* Is the guest disabling the TSC page? */
             bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
             if (!fEnable)
@@ -690 +690 @@
             }
 
-            /* Enable the TSC-page. */
+            /* Enable the TSC page. */
             RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
             int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence */, 0 /* uTscSequence */);
@@ -696 +696 @@
             {
                 pHv->u64TscPageMsr = uRawValue;
+                return VINF_SUCCESS;
+            }
+
+            return VERR_CPUM_RAISE_GP_0;
+#endif /* IN_RING3 */
+        }
+
+        case MSR_GIM_HV_APIC_ASSIST_PAGE:
+        {
+#ifndef IN_RING3
+            return VINF_CPUM_R3_MSR_WRITE;
+#else  /* IN_RING3 */
+            PGIMHVCPU pHvCpu = &pVCpu->gim.s.u.HvCpu;
+            /* First, update all but the APIC-assist page enable bit. */
+            pHvCpu->uApicAssistPageMsr = (uRawValue & ~MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT);
+
+            /* Is the guest disabling the APIC-assist page? */
+            bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_APICASSIST_PAGE_ENABLE_BIT);
+            if (!fEnable)
+            {
+                gimR3HvDisableApicAssistPage(pVM);
+                pHvCpu->uApicAssistPageMsr = uRawValue;
+                return VINF_SUCCESS;
+            }
+
+            /* Enable the APIC-assist page. */
+            RTGCPHYS GCPhysApicAssist = MSR_GIM_HV_APICASSIST_GUEST_PFN(uRawValue) << PAGE_SHIFT;
+            int rc = gimR3HvEnableApicAssistPage(pVM, GCPhysApicAssist);
+            if (RT_SUCCESS(rc))
+            {
+                pHvCpu->uApicAssistPageMsr = uRawValue;
                 return VINF_SUCCESS;
             }

trunk/src/VBox/VMM/VMMR3/GIMHv.cpp

@@ -557 +557 @@
         pVCpu->gim.s.u.HvCpu.uSint2Msr = MSR_GIM_HV_SINT_MASKED_BIT;
         pVCpu->gim.s.u.HvCpu.uSimpMsr  = 0;
+        pVCpu->gim.s.u.HvCpu.uApicAssistPageMsr = 0;
     }
 }

trunk/src/VBox/VMM/include/GIMHvInternal.h

@@ -1122 +1122 @@
     /** Interrupt source 2 MSR. */
     uint64_t                    uSint2Msr;
+    /** APIC-assist page MSR. */
+    uint64_t                    uApicAssistPageMsr;
     /** @} */
 } GIMHVCPU;