vbox的更動 62412 路徑 trunk/src/VBox/ValidationKit
- 時間撮記:
- 2016-7-21 下午08:55:46 (8 年 以前)
- 位置:
- trunk/src/VBox/ValidationKit/bootsectors
- 檔案:
-
- 修改 2 筆資料
圖例:
- 未更動
- 新增
- 刪除
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c
r62410 r62412 46 46 *********************************************************************************************************************************/ 47 47 #ifdef BS3_INSTANTIATING_CMN 48 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_mul_xBX_ud2); 48 49 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_imul_xBX_ud2); 50 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2); 49 51 extern FNBS3FAR BS3_CMN_NM(bs3CpuInstr2_idiv_xBX_ud2); 50 52 #endif … … 65 67 */ 66 68 #ifdef BS3_INSTANTIATING_CMN 69 70 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_mul)(uint8_t bMode) 71 { 72 #define MUL_CHECK_EFLAGS_ZERO (uint16_t)(X86_EFL_AF | X86_EFL_ZF) 73 #define MUL_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_PF) 74 75 static const struct 76 { 77 RTCCUINTREG uInAX; 78 RTCCUINTREG uInBX; 79 RTCCUINTREG uOutDX; 80 RTCCUINTREG uOutAX; 81 uint16_t fFlags; 82 } s_aTests[] = 83 { 84 { 1, 1, 85 0, 1, 0 }, 86 { 2, 2, 87 0, 4, 0 }, 88 { RTCCUINTREG_MAX, RTCCUINTREG_MAX, 89 RTCCUINTREG_MAX-1, 1, X86_EFL_CF | X86_EFL_OF }, 90 { RTCCINTREG_MAX, RTCCINTREG_MAX, 91 RTCCINTREG_MAX / 2, 1, X86_EFL_CF | X86_EFL_OF }, 92 { 1, RTCCUINTREG_MAX, 93 0, RTCCUINTREG_MAX, X86_EFL_PF | X86_EFL_SF }, 94 { 1, RTCCINTREG_MAX, 95 0, RTCCINTREG_MAX, X86_EFL_PF }, 96 { 2, RTCCINTREG_MAX, 97 0, RTCCUINTREG_MAX - 1, X86_EFL_SF }, 98 { RTCCINTREG_MAX + 1, 2, 99 1, 0, X86_EFL_PF | X86_EFL_CF | X86_EFL_OF }, 100 { RTCCINTREG_MAX / 2 + 1, 3, 101 0, (RTCCINTREG_MAX / 2 + 1) * 3, X86_EFL_PF | X86_EFL_SF }, 102 }; 103 104 BS3REGCTX Ctx; 105 BS3TRAPFRAME TrapFrame; 106 unsigned i, j, k; 107 108 /* Ensure the structures are allocated before we sample the stack pointer. */ 109 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 110 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 111 112 /* 113 * Create test context. 114 */ 115 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 116 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_mul_xBX_ud2)); 117 for (k = 0; k < 2; k++) 118 { 119 Ctx.rflags.u16 |= MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO; 120 for (j = 0; j < 2; j++) 121 { 122 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 123 { 124 if (k == 0) 125 { 126 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 127 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 128 } 129 else 130 { 131 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 132 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 133 } 134 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 135 if (TrapFrame.bXcpt != X86_XCPT_UD) 136 Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt); 137 else if ( TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX 138 || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX 139 || (TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO)) 140 != (s_aTests[i].fFlags & MUL_CHECK_EFLAGS) ) 141 { 142 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT, 143 i, s_aTests[i].uInAX, s_aTests[i].uInBX); 144 145 if (TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX) 146 Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 147 s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS)); 148 if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX) 149 Bs3TestFailedF("Expected xDX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 150 s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS)); 151 if ( (TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO)) 152 != (s_aTests[i].fFlags & MUL_CHECK_EFLAGS) ) 153 Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & MUL_CHECK_EFLAGS, 154 TrapFrame.Ctx.rflags.u16 & (MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO)); 155 } 156 } 157 Ctx.rflags.u16 &= ~(MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO); 158 } 159 } 160 161 return 0; 162 } 163 67 164 68 165 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_imul)(uint8_t bMode) … … 129 226 BS3REGCTX Ctx; 130 227 BS3TRAPFRAME TrapFrame; 131 unsigned i ;228 unsigned i, j, k; 132 229 133 230 /* Ensure the structures are allocated before we sample the stack pointer. */ … … 140 237 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 141 238 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_imul_xBX_ud2)); 142 Ctx.rflags.u16 |= IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO; 143 Ctx.rflags.u16 &= ~X86_EFL_PF; 144 145 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 146 { 147 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 148 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 149 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 150 if (TrapFrame.bXcpt != X86_XCPT_UD) 151 Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt); 152 else if ( TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX 153 || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX 154 || (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)) 155 != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) ) 239 240 for (k = 0; k < 2; k++) 241 { 242 Ctx.rflags.u16 |= MUL_CHECK_EFLAGS | MUL_CHECK_EFLAGS_ZERO; 243 for (j = 0; j < 2; j++) 156 244 { 157 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT, 158 i, s_aTests[i].uInAX, s_aTests[i].uInBX); 159 160 if (TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX) 161 Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 162 s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS)); 163 if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX) 164 Bs3TestFailedF("Expected xDX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 165 s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS)); 166 if ( (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)) 167 != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) ) 168 Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & IMUL_CHECK_EFLAGS, 169 TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)); 245 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 246 { 247 if (k == 0) 248 { 249 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 250 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 251 } 252 else 253 { 254 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 255 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 256 } 257 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 258 if (TrapFrame.bXcpt != X86_XCPT_UD) 259 Bs3TestFailedF("Expected #UD got %#x", TrapFrame.bXcpt); 260 else if ( TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX 261 || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX 262 || (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)) 263 != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) ) 264 { 265 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT " * %#" RTCCUINTREG_XFMT, 266 i, s_aTests[i].uInAX, s_aTests[i].uInBX); 267 268 if (TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX) 269 Bs3TestFailedF("Expected xAX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 270 s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS)); 271 if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX) 272 Bs3TestFailedF("Expected xDX = %#RX" RT_XSTR(ARCH_BITS) " got %#RX" RT_XSTR(ARCH_BITS), 273 s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS)); 274 if ( (TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)) 275 != (s_aTests[i].fFlags & IMUL_CHECK_EFLAGS) ) 276 Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", s_aTests[i].fFlags & IMUL_CHECK_EFLAGS, 277 TrapFrame.Ctx.rflags.u16 & (IMUL_CHECK_EFLAGS | IMUL_CHECK_EFLAGS_ZERO)); 278 } 279 } 170 280 } 171 281 } … … 175 285 176 286 177 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_ idiv)(uint8_t bMode)287 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_div)(uint8_t bMode) 178 288 { 179 #define IDIV_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF)289 #define DIV_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF) 180 290 static const struct 181 291 { … … 188 298 } s_aTests[] = 189 299 { 300 { 0, 1, 1, 301 1, 0, X86_XCPT_UD }, 302 { 0, 5, 2, 303 2, 1, X86_XCPT_UD }, 304 { 0, 0, 0, 305 0, 0, X86_XCPT_DE }, 306 { RTCCUINTREG_MAX, RTCCUINTREG_MAX, 0, 307 0, 0, X86_XCPT_DE }, 308 { RTCCUINTREG_MAX, RTCCUINTREG_MAX, 1, 309 0, 0, X86_XCPT_DE }, 310 { RTCCUINTREG_MAX, RTCCUINTREG_MAX, RTCCUINTREG_MAX, 311 0, 0, X86_XCPT_DE }, 312 { RTCCUINTREG_MAX - 1, RTCCUINTREG_MAX, RTCCUINTREG_MAX, 313 RTCCUINTREG_MAX, RTCCUINTREG_MAX - 1, X86_XCPT_UD }, 314 }; 315 316 BS3REGCTX Ctx; 317 BS3TRAPFRAME TrapFrame; 318 unsigned i, j; 319 320 /* Ensure the structures are allocated before we sample the stack pointer. */ 321 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 322 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 323 324 /* 325 * Create test context. 326 */ 327 Bs3RegCtxSaveEx(&Ctx, bMode, 512); 328 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, BS3_CMN_NM(bs3CpuInstr2_div_xBX_ud2)); 329 330 /* 331 * Do the tests twice, first with all flags set, then once again with 332 * flags cleared. The flags are not touched by my intel skylake CPU. 333 */ 334 Ctx.rflags.u16 |= DIV_CHECK_EFLAGS; 335 for (j = 0; j < 2; j++) 336 { 337 for (i = 0; i < RT_ELEMENTS(s_aTests); i++) 338 { 339 Ctx.rax.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInAX; 340 Ctx.rdx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInDX; 341 Ctx.rbx.RT_CONCAT(u,ARCH_BITS) = s_aTests[i].uInBX; 342 Bs3TrapSetJmpAndRestore(&Ctx, &TrapFrame); 343 344 if ( TrapFrame.bXcpt != s_aTests[i].bXcpt 345 || ( s_aTests[i].bXcpt == X86_XCPT_UD 346 ? TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutAX 347 || TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX 348 || (TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS) 349 : TrapFrame.Ctx.rax.u != Ctx.rax.u 350 || TrapFrame.Ctx.rdx.u != Ctx.rdx.u 351 || (TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS) ) ) 352 { 353 Bs3TestFailedF("test #%i failed: input %#" RTCCUINTREG_XFMT ":%" RTCCUINTREG_XFMT " / %#" RTCCUINTREG_XFMT, 354 i, s_aTests[i].uInDX, s_aTests[i].uInAX, s_aTests[i].uInBX); 355 if (TrapFrame.bXcpt != s_aTests[i].bXcpt) 356 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", s_aTests[i].bXcpt, TrapFrame.bXcpt); 357 if (s_aTests[i].bXcpt == X86_XCPT_UD) 358 { 359 if (TrapFrame.Ctx.rax.RT_CONCAT(u, ARCH_BITS) != s_aTests[i].uOutAX) 360 Bs3TestFailedF("Expected xAX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT, 361 s_aTests[i].uOutAX, TrapFrame.Ctx.rax.RT_CONCAT(u,ARCH_BITS)); 362 if (TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS) != s_aTests[i].uOutDX) 363 Bs3TestFailedF("Expected xDX = %#" RTCCUINTREG_XFMT ", got %#" RTCCUINTREG_XFMT, 364 s_aTests[i].uOutDX, TrapFrame.Ctx.rdx.RT_CONCAT(u,ARCH_BITS)); 365 if ((TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS) != (Ctx.rflags.u16 & DIV_CHECK_EFLAGS)) 366 Bs3TestFailedF("Expected EFLAGS = %#06RX16, got %#06RX16", 367 Ctx.rflags.u16 & DIV_CHECK_EFLAGS, TrapFrame.Ctx.rflags.u16 & DIV_CHECK_EFLAGS); 368 } 369 } 370 } 371 Ctx.rflags.u16 &= ~DIV_CHECK_EFLAGS; 372 } 373 374 return 0; 375 } 376 377 378 379 BS3_DECL_FAR(uint8_t) BS3_CMN_NM(bs3CpuInstr2_idiv)(uint8_t bMode) 380 { 381 #define IDIV_CHECK_EFLAGS (uint16_t)(X86_EFL_CF | X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF) 382 static const struct 383 { 384 RTCCUINTREG uInDX; 385 RTCCUINTREG uInAX; 386 RTCCUINTREG uInBX; 387 RTCCUINTREG uOutAX; 388 RTCCUINTREG uOutDX; 389 uint8_t bXcpt; 390 } s_aTests[] = 391 { 392 { 0, 0, 0, 393 0, 0, X86_XCPT_DE }, 394 { RTCCINTREG_MAX, RTCCINTREG_MAX, 0, 395 0, 0, X86_XCPT_DE }, 190 396 /* two positive values. */ 191 397 { 0, 1, 1, -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2.c
r62410 r62412 35 35 * Internal Functions * 36 36 *********************************************************************************************************************************/ 37 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_mul); 37 38 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_imul); 39 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_div); 38 40 BS3TESTMODE_PROTOTYPES_CMN(bs3CpuInstr2_idiv); 39 41 … … 44 46 static const BS3TESTMODEENTRY g_aModeTests[] = 45 47 { 48 BS3TESTMODEENTRY_CMN("mul", bs3CpuInstr2_mul), 46 49 BS3TESTMODEENTRY_CMN("imul", bs3CpuInstr2_imul), 50 BS3TESTMODEENTRY_CMN("div", bs3CpuInstr2_div), 47 51 BS3TESTMODEENTRY_CMN("idiv", bs3CpuInstr2_idiv), 48 52 };
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