儲存庫 vbox 的更動 62617
- 時間撮記:
- 2016-7-28 上午11:09:43 (8 年 以前)
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- 修改 1 筆資料
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trunk/src/VBox/Devices/Network/DevE1000.cpp
r62587 r62617 2273 2273 #else 2274 2274 pStatus->fIXSM = true; 2275 RT_NOREF_PV(pThis); RT_NOREF_PV(pFrame); RT_NOREF_PV(cb); 2275 2276 #endif 2276 2277 return VINF_SUCCESS; … … 2372 2373 E1K_INC_ISTAT_CNT(pThis->uStatRxFrm); 2373 2374 2374 # ifdef E1K_WITH_RXD_CACHE2375 # ifdef E1K_WITH_RXD_CACHE 2375 2376 while (cb > 0) 2376 2377 { … … 2384 2385 break; 2385 2386 } 2386 # else /* !E1K_WITH_RXD_CACHE */2387 # else /* !E1K_WITH_RXD_CACHE */ 2387 2388 if (RDH == RDT) 2388 2389 { … … 2397 2398 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), 2398 2399 &desc, sizeof(desc)); 2399 # endif /* !E1K_WITH_RXD_CACHE */2400 # endif /* !E1K_WITH_RXD_CACHE */ 2400 2401 if (pDesc->u64BufAddr) 2401 2402 { … … 2429 2430 e1kCsRxLeave(pThis); 2430 2431 e1kStoreRxFragment(pThis, pDesc, ptr, cb); 2431 # ifdef E1K_WITH_RXD_CACHE2432 # ifdef E1K_WITH_RXD_CACHE 2432 2433 rc = e1kCsRxEnter(pThis, VERR_SEM_BUSY); 2433 2434 if (RT_UNLIKELY(rc != VINF_SUCCESS)) 2434 2435 return rc; 2435 2436 cb = 0; 2436 # else /* !E1K_WITH_RXD_CACHE */2437 # else /* !E1K_WITH_RXD_CACHE */ 2437 2438 pThis->led.Actual.s.fReading = 0; 2438 2439 return VINF_SUCCESS; 2439 # endif /* !E1K_WITH_RXD_CACHE */2440 # endif /* !E1K_WITH_RXD_CACHE */ 2440 2441 } 2441 2442 /* … … 2444 2445 */ 2445 2446 } 2446 # ifdef E1K_WITH_RXD_CACHE2447 # ifdef E1K_WITH_RXD_CACHE 2447 2448 /* Write back the descriptor. */ 2448 2449 pDesc->status.fDD = true; 2449 2450 e1kRxDPut(pThis, pDesc); 2450 # else /* !E1K_WITH_RXD_CACHE */2451 # else /* !E1K_WITH_RXD_CACHE */ 2451 2452 else 2452 2453 { … … 2458 2459 e1kAdvanceRDH(pThis); 2459 2460 } 2460 # endif /* !E1K_WITH_RXD_CACHE */2461 # endif /* !E1K_WITH_RXD_CACHE */ 2461 2462 } 2462 2463 … … 2467 2468 2468 2469 e1kCsRxLeave(pThis); 2469 # ifdef E1K_WITH_RXD_CACHE2470 # ifdef E1K_WITH_RXD_CACHE 2470 2471 /* Complete packet has been stored -- it is time to let the guest know. */ 2471 # ifdef E1K_USE_RX_TIMERS2472 # ifdef E1K_USE_RX_TIMERS 2472 2473 if (RDTR) 2473 2474 { … … 2480 2481 else 2481 2482 { 2482 # endif /* E1K_USE_RX_TIMERS */2483 # endif /* E1K_USE_RX_TIMERS */ 2483 2484 /* 0 delay means immediate interrupt */ 2484 2485 E1K_INC_ISTAT_CNT(pThis->uStatIntRx); 2485 2486 e1kRaiseInterrupt(pThis, VERR_SEM_BUSY, ICR_RXT0); 2486 # ifdef E1K_USE_RX_TIMERS2487 } 2488 # endif /* E1K_USE_RX_TIMERS */2489 # endif /* E1K_WITH_RXD_CACHE */2487 # ifdef E1K_USE_RX_TIMERS 2488 } 2489 # endif /* E1K_USE_RX_TIMERS */ 2490 # endif /* E1K_WITH_RXD_CACHE */ 2490 2491 2491 2492 return VINF_SUCCESS; 2492 #else 2493 #else /* !IN_RING3 */ 2494 RT_NOREF_PV(pThis); RT_NOREF_PV(pvBuf); RT_NOREF_PV(cb); RT_NOREF_PV(status); 2493 2495 return VERR_INTERNAL_ERROR_2; 2494 #endif 2496 #endif /* !IN_RING3 */ 2495 2497 } 2496 2498 … … 2702 2704 return VINF_SUCCESS; 2703 2705 #else /* !IN_RING3 */ 2706 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value); 2704 2707 return VINF_IOM_R3_MMIO_WRITE; 2705 2708 #endif /* !IN_RING3 */ … … 2739 2742 return rc; 2740 2743 #else /* !IN_RING3 */ 2744 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(pu32Value); 2741 2745 return VINF_IOM_R3_MMIO_READ; 2742 2746 #endif /* !IN_RING3 */ … … 2774 2778 return VINF_SUCCESS; 2775 2779 #else /* !IN_RING3 */ 2780 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value); 2776 2781 return VINF_IOM_R3_MMIO_WRITE; 2777 2782 #endif /* !IN_RING3 */ … … 2847 2852 ICR &= ~value; 2848 2853 2854 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); 2849 2855 return VINF_SUCCESS; 2850 2856 } … … 2930 2936 static int e1kRegWriteICS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value) 2931 2937 { 2938 RT_NOREF_PV(offset); RT_NOREF_PV(index); 2932 2939 E1K_INC_ISTAT_CNT(pThis->uStatIntICS); 2933 2940 return e1kRaiseInterrupt(pThis, VINF_IOM_R3_MMIO_WRITE, value & g_aE1kRegMap[ICS_IDX].writable); … … 2948 2955 static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value) 2949 2956 { 2957 RT_NOREF_PV(offset); RT_NOREF_PV(index); 2958 2950 2959 IMS |= value; 2951 2960 E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT)); … … 2970 2979 static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value) 2971 2980 { 2981 RT_NOREF_PV(offset); RT_NOREF_PV(index); 2982 2972 2983 int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE); 2973 2984 if (RT_UNLIKELY(rc != VINF_SUCCESS)) … … 5548 5559 static int e1kRegReadDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value) 5549 5560 { 5561 RT_NOREF_PV(offset); 5562 5550 5563 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR); 5551 5564 *pu32Value = pThis->auRegs[index] & g_aE1kRegMap[index].readable; … … 5568 5581 static int e1kRegWriteUnimplemented(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value) 5569 5582 { 5583 RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index); RT_NOREF_PV(value); 5584 5570 5585 E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n", 5571 5586 pThis->szPrf, offset, value, g_aE1kRegMap[index].abbrev, g_aE1kRegMap[index].name)); … … 5592 5607 static int e1kRegWriteDefault(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value) 5593 5608 { 5609 RT_NOREF_PV(offset); 5610 5594 5611 AssertReturn(index < E1K_NUM_OF_32BIT_REGS, VERR_DEV_IO_ERROR); 5595 5612 pThis->auRegs[index] = (value & g_aE1kRegMap[index].writable) … … 5604 5621 * @returns Index in the register table or -1 if not found. 5605 5622 * 5606 * @param pThis The device state structure.5607 5623 * @param offReg Register offset in memory-mapped region. 5608 5624 * @thread EMT 5609 5625 */ 5610 static int e1kRegLookup(PE1KSTATE pThis, uint32_t offReg) 5611 { 5626 static int e1kRegLookup(uint32_t offReg) 5627 { 5628 5612 5629 #if 0 5613 5630 int index; … … 5679 5696 uint32_t shift; 5680 5697 int rc = VINF_SUCCESS; 5681 int index = e1kRegLookup( pThis,offReg);5698 int index = e1kRegLookup(offReg); 5682 5699 #ifdef LOG_ENABLED 5683 5700 char buf[9]; … … 5768 5785 */ 5769 5786 int rc = VINF_SUCCESS; 5770 int idxReg = e1kRegLookup( pThis,offReg);5787 int idxReg = e1kRegLookup(offReg); 5771 5788 if (RT_LIKELY(idxReg != -1)) 5772 5789 { … … 5814 5831 { 5815 5832 int rc = VINF_SUCCESS; 5816 int index = e1kRegLookup( pThis,offReg);5833 int index = e1kRegLookup(offReg); 5817 5834 if (RT_LIKELY(index != -1)) 5818 5835 { … … 5897 5914 int rc; 5898 5915 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIORead), a); 5916 RT_NOREF_PV(pvUser); 5899 5917 5900 5918 uPort -= pThis->IOPortBase; … … 5941 5959 int rc; 5942 5960 STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatIOWrite), a); 5961 RT_NOREF_PV(pvUser); 5943 5962 5944 5963 E1kLog2(("%s e1kIOPortOut: uPort=%RTiop value=%08x\n", pThis->szPrf, uPort, u32));
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