儲存庫 vbox 的更動 65876
- 時間撮記:
- 2017-2-25 上午12:47:44 (8 年 以前)
- 位置:
- trunk
- 檔案:
-
- 修改 6 筆資料
-
include/VBox/disopcode.h (修改) (1 筆差異)
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src/VBox/Disassembler/DisasmTables.cpp (修改) (20 筆差異)
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src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h (修改) (241 筆差異)
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src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (修改) (42 筆差異)
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src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (修改) (3 筆差異)
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src/VBox/VMM/include/IEMInternal.h (修改) (2 筆差異)
圖例:
- 未更動
- 新增
- 刪除
-
trunk/include/VBox/disopcode.h
r61135 r65876 880 880 }; 881 881 882 883 /* 8-bit GRP aliases (for IEM). */ 884 #define OP_PARM_AL OP_PARM_REG_AL 885 886 /* GPR aliases for op-size specified register sizes (for IEM). */ 887 #define OP_PARM_rAX OP_PARM_REG_EAX 888 #define OP_PARM_rCX OP_PARM_REG_ECX 889 #define OP_PARM_rDX OP_PARM_REG_EDX 890 #define OP_PARM_rBX OP_PARM_REG_EBX 891 #define OP_PARM_rSP OP_PARM_REG_ESP 892 #define OP_PARM_rBP OP_PARM_REG_EBP 893 #define OP_PARM_rSI OP_PARM_REG_ESI 894 #define OP_PARM_rDI OP_PARM_REG_EDI 895 896 /* SREG aliases (for IEM). */ 897 #define OP_PARM_ES OP_PARM_REG_ES 898 #define OP_PARM_CS OP_PARM_REG_CS 899 #define OP_PARM_SS OP_PARM_REG_SS 900 #define OP_PARM_DS OP_PARM_REG_DS 901 #define OP_PARM_FS OP_PARM_REG_FS 902 #define OP_PARM_GS OP_PARM_REG_GS 903 882 904 /* 883 905 * Note! We don't document anything here if we can help it, because it we love -
trunk/src/VBox/Disassembler/DisasmTables.cpp
r65860 r65876 86 86 { 87 87 /* 0 */ 88 OP("add %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),89 OP("add %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),90 OP("add %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),91 OP("add %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),92 OP("add AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_ADD, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),93 OP("add %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_ADD, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),94 OP("push ES", IDX_ParseFixedReg, 0, 0,OP_PUSH, OP_PARM_REG_ES, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64),95 OP("pop ES", IDX_ParseFixedReg, 0, 0,OP_POP, OP_PARM_REG_ES, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64),96 OP("or %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),97 OP("or %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),98 OP("or %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),99 OP("or %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),100 OP("or AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_OR, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),101 OP("or %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_OR, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),102 OP("push CS", IDX_ParseFixedReg, 0, 0,OP_PUSH, OP_PARM_REG_CS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_POTENTIALLY_DANGEROUS | DISOPTYPE_INVALID_64),103 OP("2-BYTE ESCAPE", IDX_ParseTwoByteEsc, 0, 0,OP_2B_ESC, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),88 OP("add %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 89 OP("add %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 90 OP("add %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 91 OP("add %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADD, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 92 OP("add AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_ADD, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 93 OP("add %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_ADD, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 94 OP("push ES", IDX_ParseFixedReg, 0, 0, OP_PUSH, OP_PARM_REG_ES, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64), 95 OP("pop ES", IDX_ParseFixedReg, 0, 0, OP_POP, OP_PARM_REG_ES, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64), 96 OP("or %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 97 OP("or %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 98 OP("or %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 99 OP("or %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_OR, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 100 OP("or AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_OR, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 101 OP("or %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_OR, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 102 OP("push CS", IDX_ParseFixedReg, 0, 0, OP_PUSH, OP_PARM_REG_CS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_POTENTIALLY_DANGEROUS | DISOPTYPE_INVALID_64), 103 OP("2-BYTE ESCAPE", IDX_ParseTwoByteEsc, 0, 0, OP_2B_ESC, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 104 104 105 105 /* 1 */ 106 OP("adc %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),107 OP("adc %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),108 OP("adc %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),109 OP("adc %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),110 OP("adc AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_ADC, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),111 OP("adc %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_ADC, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),112 OP("push SS", IDX_ParseFixedReg, 0, 0,OP_PUSH, OP_PARM_REG_SS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INVALID_64),113 OP("pop SS", IDX_ParseFixedReg, 0, 0,OP_POP, OP_PARM_REG_SS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INHIBIT_IRQS | DISOPTYPE_INVALID_64),114 OP("sbb %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),115 OP("sbb %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),116 OP("sbb %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),117 OP("sbb %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),118 OP("sbb AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_SBB, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),119 OP("sbb %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_SBB, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),120 OP("push DS", IDX_ParseFixedReg, 0, 0,OP_PUSH, OP_PARM_REG_DS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64),121 OP("pop DS", IDX_ParseFixedReg, 0, 0,OP_POP, OP_PARM_REG_DS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INVALID_64),106 OP("adc %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 107 OP("adc %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 108 OP("adc %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 109 OP("adc %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_ADC, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 110 OP("adc AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_ADC, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 111 OP("adc %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_ADC, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 112 OP("push SS", IDX_ParseFixedReg, 0, 0, OP_PUSH, OP_PARM_REG_SS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INVALID_64), 113 OP("pop SS", IDX_ParseFixedReg, 0, 0, OP_POP, OP_PARM_REG_SS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INHIBIT_IRQS | DISOPTYPE_INVALID_64), 114 OP("sbb %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 115 OP("sbb %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 116 OP("sbb %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 117 OP("sbb %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_SBB, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 118 OP("sbb AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_SBB, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 119 OP("sbb %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_SBB, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 120 OP("push DS", IDX_ParseFixedReg, 0, 0, OP_PUSH, OP_PARM_REG_DS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64), 121 OP("pop DS", IDX_ParseFixedReg, 0, 0, OP_POP, OP_PARM_REG_DS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_RRM_DANGEROUS | DISOPTYPE_INVALID_64), 122 122 123 123 /* 2 */ 124 OP("and %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),125 OP("and %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),126 OP("and %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),127 OP("and %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),128 OP("and AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_AND, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),129 OP("and %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_AND, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),124 OP("and %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 125 OP("and %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 126 OP("and %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 127 OP("and %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_AND, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 128 OP("and AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_AND, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 129 OP("and %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_AND, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 130 130 OP("SEG ES", 0, 0, 0, OP_SEG, OP_PARM_REG_ES, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 131 131 OP("daa", 0, 0, 0, OP_DAA, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64), 132 OP("sub %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Eb, OP_PARM_Gb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),133 OP("sub %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Ev, OP_PARM_Gv ,OP_PARM_NONE, DISOPTYPE_HARMLESS),134 OP("sub %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Gb, OP_PARM_Eb ,OP_PARM_NONE, DISOPTYPE_HARMLESS),135 OP("sub %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Gv, OP_PARM_Ev ,OP_PARM_NONE, DISOPTYPE_HARMLESS),136 OP("sub AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_SUB, OP_PARM_REG_AL, OP_PARM_Ib ,OP_PARM_NONE, DISOPTYPE_HARMLESS),137 OP("sub %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_SUB, OP_PARM_REG_EAX, OP_PARM_Iz ,OP_PARM_NONE, DISOPTYPE_HARMLESS),132 OP("sub %Eb,%Gb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Eb, OP_PARM_Gb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 133 OP("sub %Ev,%Gv", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Ev, OP_PARM_Gv, OP_PARM_NONE, DISOPTYPE_HARMLESS), 134 OP("sub %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 135 OP("sub %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_SUB, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 136 OP("sub AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_SUB, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 137 OP("sub %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_SUB, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 138 138 /* Branch not taken hint prefix for branches on a Pentium 4 or Xeon CPU (or higher)! */ 139 139 OP("SEG CS", 0, 0, 0, OP_SEG, OP_PARM_REG_CS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), … … 145 145 OP("xor %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_XOR, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 146 146 OP("xor %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_XOR, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 147 OP("xor AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0,OP_XOR, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),147 OP("xor AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_XOR, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 148 148 OP("xor %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_XOR, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 149 149 OP("SEG SS", 0, 0, 0, OP_SEG, OP_PARM_REG_SS, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), … … 153 153 OP("cmp %Gb,%Eb", IDX_ParseModRM, IDX_UseModRM, 0, OP_CMP, OP_PARM_Gb, OP_PARM_Eb, OP_PARM_NONE, DISOPTYPE_HARMLESS), 154 154 OP("cmp %Gv,%Ev", IDX_ParseModRM, IDX_UseModRM, 0, OP_CMP, OP_PARM_Gv, OP_PARM_Ev, OP_PARM_NONE, DISOPTYPE_HARMLESS), 155 OP("cmp AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0,OP_CMP, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),155 OP("cmp AL,%Ib", IDX_ParseFixedReg, IDX_ParseImmByte, 0, OP_CMP, OP_PARM_REG_AL, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 156 156 OP("cmp %eAX,%Iz", IDX_ParseFixedReg, IDX_ParseImmZ, 0, OP_CMP, OP_PARM_REG_EAX, OP_PARM_Iz, OP_PARM_NONE, DISOPTYPE_HARMLESS), 157 157 /* Branch not taken hint prefix for branches on a Pentium 4 or Xeon CPU (or higher)! */ … … 460 460 INVALID_OPCODE, 461 461 OP("getsec", 0, 0, 0, OP_GETSEC, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 462 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0,0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),463 INVALID_OPCODE, 464 OP("3 byte escape A5", IDX_ParseThreeByteEsc5, 0,0, OP_3B_ESC5, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),462 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0, 0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 463 INVALID_OPCODE, 464 OP("3 byte escape A5", IDX_ParseThreeByteEsc5, 0, 0, OP_3B_ESC5, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 465 465 INVALID_OPCODE, 466 466 /* SSE2 */ … … 739 739 INVALID_OPCODE, 740 740 INVALID_OPCODE, 741 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0,0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),742 INVALID_OPCODE, 743 OP("3 byte escape A5", IDX_ParseThreeByteEsc5, 0,0, OP_3B_ESC5, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),741 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0, 0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 742 INVALID_OPCODE, 743 OP("3 byte escape A5", IDX_ParseThreeByteEsc5, 0, 0, OP_3B_ESC5, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 744 744 INVALID_OPCODE, 745 745 INVALID_OPCODE, … … 941 941 INVALID_OPCODE, 942 942 INVALID_OPCODE, 943 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0,0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS),943 OP("3 byte escape A4", IDX_ParseThreeByteEsc4, 0, 0, OP_3B_ESC4, OP_PARM_NONE, OP_PARM_NONE, OP_PARM_NONE, DISOPTYPE_HARMLESS), 944 944 INVALID_OPCODE, 945 945 INVALID_OPCODE, … … 2342 2342 2343 2343 /* d */ 2344 OP("fcmovbe ST(0),ST(0)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2345 OP("fcmovbe ST(0),ST(1)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2346 OP("fcmovbe ST(0),ST(2)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2347 OP("fcmovbe ST(0),ST(3)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2348 OP("fcmovbe ST(0),ST(4)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2349 OP("fcmovbe ST(0),ST(5)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2350 OP("fcmovbe ST(0),ST(6)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2351 OP("fcmovbe ST(0),ST(7)", 0,0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2344 OP("fcmovbe ST(0),ST(0)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2345 OP("fcmovbe ST(0),ST(1)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2346 OP("fcmovbe ST(0),ST(2)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2347 OP("fcmovbe ST(0),ST(3)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2348 OP("fcmovbe ST(0),ST(4)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2349 OP("fcmovbe ST(0),ST(5)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2350 OP("fcmovbe ST(0),ST(6)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2351 OP("fcmovbe ST(0),ST(7)", 0, 0, 0, OP_FCMOVBE, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2352 2352 OP("fcmovu ST(0),ST(0)", 0, 0, 0, OP_FCMOVU, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2353 2353 OP("fcmovu ST(0),ST(1)", 0, 0, 0, OP_FCMOVU, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), … … 2401 2401 { 2402 2402 /* c */ 2403 OP("fcmovnb ST(0),ST(0)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2404 OP("fcmovnb ST(0),ST(1)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2405 OP("fcmovnb ST(0),ST(2)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2406 OP("fcmovnb ST(0),ST(3)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2407 OP("fcmovnb ST(0),ST(4)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2408 OP("fcmovnb ST(0),ST(5)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2409 OP("fcmovnb ST(0),ST(6)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2410 OP("fcmovnb ST(0),ST(7)", 0,0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2411 OP("fcmovne ST(0),ST(0)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2412 OP("fcmovne ST(0),ST(1)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2413 OP("fcmovne ST(0),ST(2)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2414 OP("fcmovne ST(0),ST(3)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2415 OP("fcmovne ST(0),ST(4)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2416 OP("fcmovne ST(0),ST(5)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2417 OP("fcmovne ST(0),ST(6)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2418 OP("fcmovne ST(0),ST(7)", 0,0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2403 OP("fcmovnb ST(0),ST(0)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2404 OP("fcmovnb ST(0),ST(1)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2405 OP("fcmovnb ST(0),ST(2)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2406 OP("fcmovnb ST(0),ST(3)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2407 OP("fcmovnb ST(0),ST(4)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2408 OP("fcmovnb ST(0),ST(5)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2409 OP("fcmovnb ST(0),ST(6)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2410 OP("fcmovnb ST(0),ST(7)", 0, 0, 0, OP_FCMOVNB, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2411 OP("fcmovne ST(0),ST(0)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2412 OP("fcmovne ST(0),ST(1)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2413 OP("fcmovne ST(0),ST(2)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2414 OP("fcmovne ST(0),ST(3)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2415 OP("fcmovne ST(0),ST(4)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2416 OP("fcmovne ST(0),ST(5)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2417 OP("fcmovne ST(0),ST(6)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2418 OP("fcmovne ST(0),ST(7)", 0, 0, 0, OP_FCMOVNE, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2419 2419 2420 2420 /* d */ 2421 OP("fcmovnbe ST(0),ST(0)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2422 OP("fcmovnbe ST(0),ST(1)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2423 OP("fcmovnbe ST(0),ST(2)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2424 OP("fcmovnbe ST(0),ST(3)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2425 OP("fcmovnbe ST(0),ST(4)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2426 OP("fcmovnbe ST(0),ST(5)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2427 OP("fcmovnbe ST(0),ST(6)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2428 OP("fcmovnbe ST(0),ST(7)", 0,0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2429 OP("fcmovnu ST(0),ST(0)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2430 OP("fcmovnu ST(0),ST(1)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2431 OP("fcmovnu ST(0),ST(2)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2432 OP("fcmovnu ST(0),ST(3)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2433 OP("fcmovnu ST(0),ST(4)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2434 OP("fcmovnu ST(0),ST(5)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2435 OP("fcmovnu ST(0),ST(6)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2436 OP("fcmovnu ST(0),ST(7)", 0,0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2421 OP("fcmovnbe ST(0),ST(0)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2422 OP("fcmovnbe ST(0),ST(1)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2423 OP("fcmovnbe ST(0),ST(2)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2424 OP("fcmovnbe ST(0),ST(3)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2425 OP("fcmovnbe ST(0),ST(4)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2426 OP("fcmovnbe ST(0),ST(5)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2427 OP("fcmovnbe ST(0),ST(6)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2428 OP("fcmovnbe ST(0),ST(7)", 0, 0, 0, OP_FCMOVNBE,OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2429 OP("fcmovnu ST(0),ST(0)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2430 OP("fcmovnu ST(0),ST(1)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2431 OP("fcmovnu ST(0),ST(2)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2432 OP("fcmovnu ST(0),ST(3)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2433 OP("fcmovnu ST(0),ST(4)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2434 OP("fcmovnu ST(0),ST(5)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2435 OP("fcmovnu ST(0),ST(6)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2436 OP("fcmovnu ST(0),ST(7)", 0, 0, 0, OP_FCMOVNU, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2437 2437 2438 2438 /* e */ … … 2445 2445 INVALID_OPCODE, 2446 2446 INVALID_OPCODE, 2447 OP("fucomi ST(0),ST(0)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2448 OP("fucomi ST(0),ST(1)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2449 OP("fucomi ST(0),ST(2)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2450 OP("fucomi ST(0),ST(3)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2451 OP("fucomi ST(0),ST(4)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2452 OP("fucomi ST(0),ST(5)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2453 OP("fucomi ST(0),ST(6)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2454 OP("fucomi ST(0),ST(7)", 0,0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2447 OP("fucomi ST(0),ST(0)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2448 OP("fucomi ST(0),ST(1)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2449 OP("fucomi ST(0),ST(2)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2450 OP("fucomi ST(0),ST(3)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2451 OP("fucomi ST(0),ST(4)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2452 OP("fucomi ST(0),ST(5)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2453 OP("fucomi ST(0),ST(6)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2454 OP("fucomi ST(0),ST(7)", 0, 0, 0, OP_FUCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2455 2455 2456 2456 2457 2457 /* e */ 2458 OP("fcomi ST(0),ST(0)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2459 OP("fcomi ST(0),ST(1)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2460 OP("fcomi ST(0),ST(2)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2461 OP("fcomi ST(0),ST(3)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2462 OP("fcomi ST(0),ST(4)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2463 OP("fcomi ST(0),ST(5)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2464 OP("fcomi ST(0),ST(6)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2465 OP("fcomi ST(0),ST(7)", 0,0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2458 OP("fcomi ST(0),ST(0)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2459 OP("fcomi ST(0),ST(1)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2460 OP("fcomi ST(0),ST(2)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2461 OP("fcomi ST(0),ST(3)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2462 OP("fcomi ST(0),ST(4)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2463 OP("fcomi ST(0),ST(5)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2464 OP("fcomi ST(0),ST(6)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2465 OP("fcomi ST(0),ST(7)", 0, 0, 0, OP_FCOMI, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2466 2466 INVALID_OPCODE, 2467 2467 INVALID_OPCODE, … … 2757 2757 INVALID_OPCODE, 2758 2758 INVALID_OPCODE, 2759 OP("fucomip ST(0),ST(0)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS),2760 OP("fucomip ST(0),ST(1)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS),2761 OP("fucomip ST(0),ST(2)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS),2762 OP("fucomip ST(0),ST(3)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS),2763 OP("fucomip ST(0),ST(4)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS),2764 OP("fucomip ST(0),ST(5)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS),2765 OP("fucomip ST(0),ST(6)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS),2766 OP("fucomip ST(0),ST(7)", 0,0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS),2759 OP("fucomip ST(0),ST(0)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_0,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2760 OP("fucomip ST(0),ST(1)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_1,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2761 OP("fucomip ST(0),ST(2)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_2,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2762 OP("fucomip ST(0),ST(3)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_3,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2763 OP("fucomip ST(0),ST(4)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_4,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2764 OP("fucomip ST(0),ST(5)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_5,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2765 OP("fucomip ST(0),ST(6)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_6,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2766 OP("fucomip ST(0),ST(7)", 0, 0, 0, OP_FUCOMIP, OP_PARM_REGFP_0, OP_PARM_REGFP_7,OP_PARM_NONE, DISOPTYPE_HARMLESS), 2767 2767 2768 2768 /* f */ … … 2814 2814 { 2815 2815 /* 80 */ 2816 OP("add %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ADD, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2817 OP("or %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_OR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2818 OP("adc %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ADC, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2819 OP("sbb %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SBB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2820 OP("and %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_AND, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2821 OP("sub %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SUB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2822 OP("xor %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_XOR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2823 OP("cmp %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_CMP, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2816 OP("add %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ADD, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2817 OP("or %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_OR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2818 OP("adc %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ADC, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2819 OP("sbb %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SBB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2820 OP("and %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_AND, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2821 OP("sub %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SUB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2822 OP("xor %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_XOR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2823 OP("cmp %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_CMP, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2824 2824 2825 2825 /* 81 */ … … 2834 2834 2835 2835 /* 82 */ 2836 OP("add %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ADD, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2837 OP("or %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_OR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2838 OP("adc %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ADC, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2839 OP("sbb %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SBB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2840 OP("and %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_AND, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2841 OP("sub %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SUB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2842 OP("xor %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_XOR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2843 OP("cmp %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_CMP, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2836 OP("add %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ADD, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2837 OP("or %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_OR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2838 OP("adc %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ADC, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2839 OP("sbb %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SBB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2840 OP("and %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_AND, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2841 OP("sub %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SUB, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2842 OP("xor %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_XOR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2843 OP("cmp %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_CMP, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2844 2844 2845 2845 /* 83 */ 2846 OP("add %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_ADD, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2847 OP("or %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_OR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2848 OP("adc %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_ADC, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2849 OP("sbb %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_SBB, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2850 OP("and %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_AND, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2851 OP("sub %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_SUB, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2852 OP("xor %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_XOR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2853 OP("cmp %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0,OP_CMP, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2846 OP("add %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_ADD, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2847 OP("or %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_OR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2848 OP("adc %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_ADC, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2849 OP("sbb %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_SBB, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2850 OP("and %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_AND, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2851 OP("sub %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_SUB, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2852 OP("xor %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_XOR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2853 OP("cmp %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByteSX, 0, OP_CMP, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2854 2854 }; 2855 2855 … … 2857 2857 { 2858 2858 /* C0 */ 2859 OP("rol %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ROL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2860 OP("ror %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ROR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2861 OP("rcl %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_RCL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2862 OP("rcr %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_RCR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2863 OP("shl/sal %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2864 OP("shr %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2865 OP("shl/sal %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2866 OP("sar %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SAR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2859 OP("rol %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ROL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2860 OP("ror %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ROR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2861 OP("rcl %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_RCL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2862 OP("rcr %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_RCR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2863 OP("shl/sal %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2864 OP("shr %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2865 OP("shl/sal %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHL, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2866 OP("sar %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SAR, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2867 2867 2868 2868 /* C1 */ 2869 OP("rol %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ROL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2870 OP("ror %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_ROR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2871 OP("rcl %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_RCL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2872 OP("rcr %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_RCR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2873 OP("shl/sal %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2874 OP("shr %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2875 OP("shl/sal %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SHL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2876 OP("sar %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_SAR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2869 OP("rol %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ROL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2870 OP("ror %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_ROR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2871 OP("rcl %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_RCL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2872 OP("rcr %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_RCR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2873 OP("shl/sal %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2874 OP("shr %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2875 OP("shl/sal %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SHL, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2876 OP("sar %Ev,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_SAR, OP_PARM_Ev, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2877 2877 2878 2878 /* D0 */ … … 2922 2922 { 2923 2923 /* F6 */ 2924 OP("test %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_TEST, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS),2924 OP("test %Eb,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_TEST, OP_PARM_Eb, OP_PARM_Ib , OP_PARM_NONE, DISOPTYPE_HARMLESS), 2925 2925 //AMD manual claims test?? 2926 2926 INVALID_OPCODE_MOD_RM(0xf601), … … 3094 3094 INVALID_OPCODE_MOD_RM(0x), 3095 3095 INVALID_OPCODE_MOD_RM(0x), 3096 OP("psrlw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3097 INVALID_OPCODE_MOD_RM(0x), 3098 OP("psraw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRAW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3099 INVALID_OPCODE_MOD_RM(0x), 3100 OP("psllw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3096 OP("psrlw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3097 INVALID_OPCODE_MOD_RM(0x), 3098 OP("psraw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRAW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3099 INVALID_OPCODE_MOD_RM(0x), 3100 OP("psllw %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLW, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3101 3101 INVALID_OPCODE_MOD_RM(0x), 3102 3102 … … 3104 3104 INVALID_OPCODE_MOD_RM(0x), 3105 3105 INVALID_OPCODE_MOD_RM(0x), 3106 OP("psrlw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3107 INVALID_OPCODE_MOD_RM(0x), 3108 OP("psraw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRAW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3109 INVALID_OPCODE_MOD_RM(0x), 3110 OP("psllw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3106 OP("psrlw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3107 INVALID_OPCODE_MOD_RM(0x), 3108 OP("psraw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRAW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3109 INVALID_OPCODE_MOD_RM(0x), 3110 OP("psllw %Pdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLW, OP_PARM_Pdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3111 3111 INVALID_OPCODE_MOD_RM(0x), 3112 3112 }; … … 3117 3117 INVALID_OPCODE_MOD_RM(0x), 3118 3118 INVALID_OPCODE_MOD_RM(0x), 3119 OP("psrld %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3120 INVALID_OPCODE_MOD_RM(0x), 3121 OP("psrad %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRAD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3122 INVALID_OPCODE_MOD_RM(0x), 3123 OP("pslld %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3119 OP("psrld %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3120 INVALID_OPCODE_MOD_RM(0x), 3121 OP("psrad %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRAD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3122 INVALID_OPCODE_MOD_RM(0x), 3123 OP("pslld %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLD, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3124 3124 INVALID_OPCODE_MOD_RM(0x), 3125 3125 … … 3127 3127 INVALID_OPCODE_MOD_RM(0x), 3128 3128 INVALID_OPCODE_MOD_RM(0x), 3129 OP("psrld %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3130 INVALID_OPCODE_MOD_RM(0x), 3131 OP("psrad %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRAD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3132 INVALID_OPCODE_MOD_RM(0x), 3133 OP("pslld %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3129 OP("psrld %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3130 INVALID_OPCODE_MOD_RM(0x), 3131 OP("psrad %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRAD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3132 INVALID_OPCODE_MOD_RM(0x), 3133 OP("pslld %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3134 3134 INVALID_OPCODE_MOD_RM(0x), 3135 3135 }; … … 3140 3140 INVALID_OPCODE_MOD_RM(0x), 3141 3141 INVALID_OPCODE_MOD_RM(0x), 3142 OP("psrlq %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLQ, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3143 INVALID_OPCODE_MOD_RM(0x), 3144 INVALID_OPCODE_MOD_RM(0x), 3145 INVALID_OPCODE_MOD_RM(0x), 3146 OP("psllq %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLQ, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3142 OP("psrlq %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLQ, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3143 INVALID_OPCODE_MOD_RM(0x), 3144 INVALID_OPCODE_MOD_RM(0x), 3145 INVALID_OPCODE_MOD_RM(0x), 3146 OP("psllq %Pq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLQ, OP_PARM_Pq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3147 3147 INVALID_OPCODE_MOD_RM(0x), 3148 3148 … … 3150 3150 INVALID_OPCODE_MOD_RM(0x), 3151 3151 INVALID_OPCODE_MOD_RM(0x), 3152 OP("psrlq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3153 OP("psrldq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSRLDQ, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3154 INVALID_OPCODE_MOD_RM(0x), 3155 INVALID_OPCODE_MOD_RM(0x), 3156 OP("psllq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3157 OP("pslldq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0,OP_PSLLDQ, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS),3152 OP("psrlq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3153 OP("psrldq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSRLDQ, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3154 INVALID_OPCODE_MOD_RM(0x), 3155 INVALID_OPCODE_MOD_RM(0x), 3156 OP("psllq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLD, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3157 OP("pslldq %Wdq,%Ib", IDX_ParseModRM, IDX_ParseImmByte, 0, OP_PSLLDQ, OP_PARM_Wdq, OP_PARM_Ib, OP_PARM_NONE, DISOPTYPE_HARMLESS), 3158 3158 }; 3159 3159 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r65871 r65876 44 44 * @opcode 0x00 45 45 * @opmnemonic add 46 * @op1 r eg:Eb47 * @op2 r m:Gb46 * @op1 rm:Eb 47 * @op2 reg:Gb 48 48 * @opmaps one 49 49 * @openc ModR/M … … 56 56 FNIEMOP_DEF(iemOp_add_Eb_Gb) 57 57 { 58 IEMOP_MNEMONIC2( RM, ADD, add, Eb, Gb, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);58 IEMOP_MNEMONIC2(MR, ADD, add, Eb, Gb, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 59 59 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_add); 60 60 } 61 61 62 62 63 /** Opcode 0x01. */ 63 /** 64 * @opcode 0x01 65 * @opgroup op_gen_arith_bin 66 * @opflmodify of,sf,zf,af,pf,cf 67 */ 64 68 FNIEMOP_DEF(iemOp_add_Ev_Gv) 65 69 { 66 IEMOP_MNEMONIC2( RM, ADD, add, Ev, Gv, DISOPTYPE_HARMLESS, 0);70 IEMOP_MNEMONIC2(MR, ADD, add, Ev, Gv, DISOPTYPE_HARMLESS, 0); 67 71 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_add); 68 72 } 69 73 70 74 71 /** Opcode 0x02. */ 75 /** 76 * @opcode 0x02 77 * @opgroup op_gen_arith_bin 78 * @opflmodify of,sf,zf,af,pf,cf 79 */ 72 80 FNIEMOP_DEF(iemOp_add_Gb_Eb) 73 81 { 74 IEMOP_MNEMONIC2( MR, ADD, add, Gb, Ev, DISOPTYPE_HARMLESS, 0);82 IEMOP_MNEMONIC2(RM, ADD, add, Gb, Eb, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 75 83 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_add); 76 84 } 77 85 78 86 79 /** Opcode 0x03. */ 87 /** 88 * @opcode 0x03 89 * @opgroup op_gen_arith_bin 90 * @opflmodify of,sf,zf,af,pf,cf 91 */ 80 92 FNIEMOP_DEF(iemOp_add_Gv_Ev) 81 93 { 82 IEMOP_MNEMONIC (add_Gv_Ev, "add Gv,Ev");94 IEMOP_MNEMONIC2(RM, ADD, add, Gv, Ev, DISOPTYPE_HARMLESS, 0); 83 95 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_add); 84 96 } 85 97 86 98 87 /** Opcode 0x04. */ 99 /** 100 * @opcode 0x04 101 * @opgroup op_gen_arith_bin 102 * @opflmodify of,sf,zf,af,pf,cf 103 */ 88 104 FNIEMOP_DEF(iemOp_add_Al_Ib) 89 105 { 90 IEMOP_MNEMONIC (add_al_Ib, "add al,Ib");106 IEMOP_MNEMONIC2(FIXED, ADD, add, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 91 107 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_add); 92 108 } 93 109 94 110 95 /** Opcode 0x05. */ 111 /** 112 * @opcode 0x05 113 * @opgroup op_gen_arith_bin 114 * @opflmodify of,sf,zf,af,pf,cf 115 */ 96 116 FNIEMOP_DEF(iemOp_add_eAX_Iz) 97 117 { 98 IEMOP_MNEMONIC (add_rAX_Iz, "add rAX,Iz");118 IEMOP_MNEMONIC2(FIXED, ADD, add, rAX, Iz, DISOPTYPE_HARMLESS, 0); 99 119 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_add); 100 120 } 101 121 102 122 103 /** Opcode 0x06. */ 123 /** 124 * @opcode 0x06 125 * @opgroup op_stack_sreg 126 */ 104 127 FNIEMOP_DEF(iemOp_push_ES) 105 128 { 106 IEMOP_MNEMONIC(push_es, "push es"); 129 IEMOP_MNEMONIC1(FIXED, PUSH, push, ES, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64, 0); 130 IEMOP_HLP_NO_64BIT(); 107 131 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_ES); 108 132 } 109 133 110 134 111 /** Opcode 0x07. */ 135 /** 136 * @opcode 0x07 137 * @opgroup op_stack_sreg 138 */ 112 139 FNIEMOP_DEF(iemOp_pop_ES) 113 140 { 114 IEMOP_MNEMONIC (pop_es, "pop es");141 IEMOP_MNEMONIC1(FIXED, POP, pop, ES, DISOPTYPE_HARMLESS | DISOPTYPE_INVALID_64, 0); 115 142 IEMOP_HLP_NO_64BIT(); 116 143 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); … … 119 146 120 147 121 /** Opcode 0x08. */ 148 /** 149 * @opcode 0x08 150 * @opgroup op_gen_arith_bin 151 * @opflmodify of,sf,zf,af,pf,cf 152 * @opflundef af 153 * @opflclear of,cf 154 */ 122 155 FNIEMOP_DEF(iemOp_or_Eb_Gb) 123 156 { 124 IEMOP_MNEMONIC (or_Eb_Gb, "or Eb,Gb");157 IEMOP_MNEMONIC2(MR, OR, or, Eb, Gb, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 125 158 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 126 159 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_r8, &g_iemAImpl_or); … … 128 161 129 162 130 /** Opcode 0x09. */ 163 /** 164 * @opcode 0x09 165 * @opgroup op_gen_arith_bin 166 * @opflmodify of,sf,zf,af,pf,cf 167 * @opflundef af 168 * @opflclear of,cf 169 */ 131 170 FNIEMOP_DEF(iemOp_or_Ev_Gv) 132 171 { 133 IEMOP_MNEMONIC (or_Ev_Gv, "or Ev,Gv");172 IEMOP_MNEMONIC2(MR, OR, or, Ev, Gv, DISOPTYPE_HARMLESS, 0); 134 173 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 135 174 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rm_rv, &g_iemAImpl_or); … … 137 176 138 177 139 /** Opcode 0x0a. */ 178 /** 179 * @opcode 0x0a 180 * @opgroup op_gen_arith_bin 181 * @opflmodify of,sf,zf,af,pf,cf 182 * @opflundef af 183 * @opflclear of,cf 184 */ 140 185 FNIEMOP_DEF(iemOp_or_Gb_Eb) 141 186 { 142 IEMOP_MNEMONIC (or_Gb_Eb, "or Gb,Eb");187 IEMOP_MNEMONIC2(RM, OR, or, Gb, Eb, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 143 188 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 144 189 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_r8_rm, &g_iemAImpl_or); … … 146 191 147 192 148 /** Opcode 0x0b. */ 193 /** 194 * @opcode 0x0b 195 * @opgroup op_gen_arith_bin 196 * @opflmodify of,sf,zf,af,pf,cf 197 * @opflundef af 198 * @opflclear of,cf 199 */ 149 200 FNIEMOP_DEF(iemOp_or_Gv_Ev) 150 201 { 151 IEMOP_MNEMONIC (or_Gv_Ev, "or Gv,Ev");202 IEMOP_MNEMONIC2(RM, OR, or, Gv, Ev, DISOPTYPE_HARMLESS, 0); 152 203 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 153 204 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rv_rm, &g_iemAImpl_or); … … 155 206 156 207 157 /** Opcode 0x0c. */ 208 /** 209 * @opcode 0x0c 210 * @opgroup op_gen_arith_bin 211 * @opflmodify of,sf,zf,af,pf,cf 212 * @opflundef af 213 * @opflclear of,cf 214 */ 158 215 FNIEMOP_DEF(iemOp_or_Al_Ib) 159 216 { 160 IEMOP_MNEMONIC (or_al_Ib, "or al,Ib");217 IEMOP_MNEMONIC2(FIXED, OR, or, AL, Ib, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 161 218 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 162 219 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_AL_Ib, &g_iemAImpl_or); … … 164 221 165 222 166 /** Opcode 0x0d. */ 223 /** 224 * @opcode 0x0d 225 * @opgroup op_gen_arith_bin 226 * @opflmodify of,sf,zf,af,pf,cf 227 * @opflundef af 228 * @opflclear of,cf 229 */ 167 230 FNIEMOP_DEF(iemOp_or_eAX_Iz) 168 231 { 169 IEMOP_MNEMONIC (or_rAX_Iz, "or rAX,Iz");232 IEMOP_MNEMONIC2(FIXED, OR, or, rAX, Iz, DISOPTYPE_HARMLESS, 0); 170 233 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 171 234 return FNIEMOP_CALL_1(iemOpHlpBinaryOperator_rAX_Iz, &g_iemAImpl_or); … … 173 236 174 237 175 /** Opcode 0x0e. */ 238 /** 239 * @opcode 0x0e 240 * @opgroup op_stack_sreg 241 */ 176 242 FNIEMOP_DEF(iemOp_push_CS) 177 243 { 178 IEMOP_MNEMONIC(push_cs, "push cs"); 244 IEMOP_MNEMONIC1(FIXED, PUSH, push, CS, DISOPTYPE_HARMLESS | DISOPTYPE_POTENTIALLY_DANGEROUS | DISOPTYPE_INVALID_64, 0); 245 IEMOP_HLP_NO_64BIT(); 179 246 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_CS); 180 247 } 181 248 182 249 183 /** Opcode 0x0f. */ 250 /** 251 * @opcode 0x0f 252 * @mnemonic 2byteescape 253 * @encoding two0f 254 * @opdisenum OP_2B_ESC 255 * @ophints harmless 256 * @opgroup op_escapes 257 */ 184 258 FNIEMOP_DEF(iemOp_2byteEscape) 185 259 { 186 260 #ifdef VBOX_STRICT 261 /* Sanity check the table the first time around. */ 187 262 static bool s_fTested = false; 188 263 if (RT_LIKELY(s_fTested)) { /* likely */ } … … 197 272 #endif 198 273 199 uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b); 200 201 /** @todo PUSH CS on 8086, undefined on 80186. */ 202 IEMOP_HLP_MIN_286(); 203 return FNIEMOP_CALL(g_apfnTwoByteMap[(uintptr_t)b * 4 + pVCpu->iem.s.idxPrefix]); 274 if (RT_LIKELY(IEM_GET_TARGET_CPU(pVCpu) >= IEMTARGETCPU_286)) 275 { 276 uint8_t b; IEM_OPCODE_GET_NEXT_U8(&b); 277 IEMOP_HLP_MIN_286(); 278 return FNIEMOP_CALL(g_apfnTwoByteMap[(uintptr_t)b * 4 + pVCpu->iem.s.idxPrefix]); 279 } 280 281 /* 282 * On the 8086 this is a POP CS instruction. 283 * For the time being we don't specify this this. 284 */ 285 IEMOP_MNEMONIC1(FIXED, POP, pop, CS, DISOPTYPE_HARMLESS | DISOPTYPE_POTENTIALLY_DANGEROUS | DISOPTYPE_INVALID_64, IEMOPHINT_SKIP_PYTHON); 286 IEMOP_HLP_NO_64BIT(); 287 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 288 return IEM_MC_DEFER_TO_CIMPL_2(iemCImpl_pop_Sreg, X86_SREG_ES, pVCpu->iem.s.enmEffOpSize); 204 289 } 205 290 … … 226 311 227 312 228 /** Opcode 0x11. */ 313 /** 314 * @opcode 0x11 315 */ 229 316 FNIEMOP_DEF(iemOp_adc_Ev_Gv) 230 317 { … … 234 321 235 322 236 /** Opcode 0x12. */ 323 /** 324 * @opcode 0x12 325 */ 237 326 FNIEMOP_DEF(iemOp_adc_Gb_Eb) 238 327 { … … 242 331 243 332 244 /** Opcode 0x13. */ 333 /** 334 * @opcode 0x13 335 */ 245 336 FNIEMOP_DEF(iemOp_adc_Gv_Ev) 246 337 { … … 250 341 251 342 252 /** Opcode 0x14. */ 343 /** 344 * @opcode 0x14 345 */ 253 346 FNIEMOP_DEF(iemOp_adc_Al_Ib) 254 347 { … … 258 351 259 352 260 /** Opcode 0x15. */ 353 /** 354 * @opcode 0x15 355 */ 261 356 FNIEMOP_DEF(iemOp_adc_eAX_Iz) 262 357 { … … 266 361 267 362 268 /** Opcode 0x16. */ 363 /** 364 * @opcode 0x16 365 */ 269 366 FNIEMOP_DEF(iemOp_push_SS) 270 367 { 271 368 IEMOP_MNEMONIC(push_ss, "push ss"); 369 IEMOP_HLP_NO_64BIT(); 272 370 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_SS); 273 371 } 274 372 275 373 276 /** Opcode 0x17. */ 374 /** 375 * @opcode 0x17 376 */ 277 377 FNIEMOP_DEF(iemOp_pop_SS) 278 378 { … … 284 384 285 385 286 /** Opcode 0x18. */ 386 /** 387 * @opcode 0x18 388 */ 287 389 FNIEMOP_DEF(iemOp_sbb_Eb_Gb) 288 390 { … … 292 394 293 395 294 /** Opcode 0x19. */ 396 /** 397 * @opcode 0x19 398 */ 295 399 FNIEMOP_DEF(iemOp_sbb_Ev_Gv) 296 400 { … … 300 404 301 405 302 /** Opcode 0x1a. */ 406 /** 407 * @opcode 0x1a 408 */ 303 409 FNIEMOP_DEF(iemOp_sbb_Gb_Eb) 304 410 { … … 308 414 309 415 310 /** Opcode 0x1b. */ 416 /** 417 * @opcode 0x1b 418 */ 311 419 FNIEMOP_DEF(iemOp_sbb_Gv_Ev) 312 420 { … … 316 424 317 425 318 /** Opcode 0x1c. */ 426 /** 427 * @opcode 0x1c 428 */ 319 429 FNIEMOP_DEF(iemOp_sbb_Al_Ib) 320 430 { … … 324 434 325 435 326 /** Opcode 0x1d. */ 436 /** 437 * @opcode 0x1d 438 */ 327 439 FNIEMOP_DEF(iemOp_sbb_eAX_Iz) 328 440 { … … 332 444 333 445 334 /** Opcode 0x1e. */ 446 /** 447 * @opcode 0x1e 448 */ 335 449 FNIEMOP_DEF(iemOp_push_DS) 336 450 { 337 451 IEMOP_MNEMONIC(push_ds, "push ds"); 452 IEMOP_HLP_NO_64BIT(); 338 453 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_DS); 339 454 } 340 455 341 456 342 /** Opcode 0x1f. */ 457 /** 458 * @opcode 0x1f 459 */ 343 460 FNIEMOP_DEF(iemOp_pop_DS) 344 461 { … … 350 467 351 468 352 /** Opcode 0x20. */ 469 /** 470 * @opcode 0x20 471 */ 353 472 FNIEMOP_DEF(iemOp_and_Eb_Gb) 354 473 { … … 359 478 360 479 361 /** Opcode 0x21. */ 480 /** 481 * @opcode 0x21 482 */ 362 483 FNIEMOP_DEF(iemOp_and_Ev_Gv) 363 484 { … … 368 489 369 490 370 /** Opcode 0x22. */ 491 /** 492 * @opcode 0x22 493 */ 371 494 FNIEMOP_DEF(iemOp_and_Gb_Eb) 372 495 { … … 377 500 378 501 379 /** Opcode 0x23. */ 502 /** 503 * @opcode 0x23 504 */ 380 505 FNIEMOP_DEF(iemOp_and_Gv_Ev) 381 506 { … … 386 511 387 512 388 /** Opcode 0x24. */ 513 /** 514 * @opcode 0x24 515 */ 389 516 FNIEMOP_DEF(iemOp_and_Al_Ib) 390 517 { … … 395 522 396 523 397 /** Opcode 0x25. */ 524 /** 525 * @opcode 0x25 526 */ 398 527 FNIEMOP_DEF(iemOp_and_eAX_Iz) 399 528 { … … 404 533 405 534 406 /** Opcode 0x26. */ 535 /** 536 * @opcode 0x26 537 */ 407 538 FNIEMOP_DEF(iemOp_seg_ES) 408 539 { … … 416 547 417 548 418 /** Opcode 0x27. */ 549 /** 550 * @opcode 0x27 551 */ 419 552 FNIEMOP_DEF(iemOp_daa) 420 553 { … … 427 560 428 561 429 /** Opcode 0x28. */ 562 /** 563 * @opcode 0x28 564 */ 430 565 FNIEMOP_DEF(iemOp_sub_Eb_Gb) 431 566 { … … 435 570 436 571 437 /** Opcode 0x29. */ 572 /** 573 * @opcode 0x29 574 */ 438 575 FNIEMOP_DEF(iemOp_sub_Ev_Gv) 439 576 { … … 443 580 444 581 445 /** Opcode 0x2a. */ 582 /** 583 * @opcode 0x2a 584 */ 446 585 FNIEMOP_DEF(iemOp_sub_Gb_Eb) 447 586 { … … 451 590 452 591 453 /** Opcode 0x2b. */ 592 /** 593 * @opcode 0x2b 594 */ 454 595 FNIEMOP_DEF(iemOp_sub_Gv_Ev) 455 596 { … … 459 600 460 601 461 /** Opcode 0x2c. */ 602 /** 603 * @opcode 0x2c 604 */ 462 605 FNIEMOP_DEF(iemOp_sub_Al_Ib) 463 606 { … … 467 610 468 611 469 /** Opcode 0x2d. */ 612 /** 613 * @opcode 0x2d 614 */ 470 615 FNIEMOP_DEF(iemOp_sub_eAX_Iz) 471 616 { … … 475 620 476 621 477 /** Opcode 0x2e. */ 622 /** 623 * @opcode 0x2e 624 */ 478 625 FNIEMOP_DEF(iemOp_seg_CS) 479 626 { … … 487 634 488 635 489 /** Opcode 0x2f. */ 636 /** 637 * @opcode 0x2f 638 */ 490 639 FNIEMOP_DEF(iemOp_das) 491 640 { … … 498 647 499 648 500 /** Opcode 0x30. */ 649 /** 650 * @opcode 0x30 651 */ 501 652 FNIEMOP_DEF(iemOp_xor_Eb_Gb) 502 653 { … … 507 658 508 659 509 /** Opcode 0x31. */ 660 /** 661 * @opcode 0x31 662 */ 510 663 FNIEMOP_DEF(iemOp_xor_Ev_Gv) 511 664 { … … 516 669 517 670 518 /** Opcode 0x32. */ 671 /** 672 * @opcode 0x32 673 */ 519 674 FNIEMOP_DEF(iemOp_xor_Gb_Eb) 520 675 { … … 525 680 526 681 527 /** Opcode 0x33. */ 682 /** 683 * @opcode 0x33 684 */ 528 685 FNIEMOP_DEF(iemOp_xor_Gv_Ev) 529 686 { … … 534 691 535 692 536 /** Opcode 0x34. */ 693 /** 694 * @opcode 0x34 695 */ 537 696 FNIEMOP_DEF(iemOp_xor_Al_Ib) 538 697 { … … 543 702 544 703 545 /** Opcode 0x35. */ 704 /** 705 * @opcode 0x35 706 */ 546 707 FNIEMOP_DEF(iemOp_xor_eAX_Iz) 547 708 { … … 552 713 553 714 554 /** Opcode 0x36. */ 715 /** 716 * @opcode 0x36 717 */ 555 718 FNIEMOP_DEF(iemOp_seg_SS) 556 719 { … … 564 727 565 728 566 /** Opcode 0x37. */ 729 /** 730 * @opcode 0x37 731 */ 567 732 FNIEMOP_STUB(iemOp_aaa); 568 733 569 734 570 /** Opcode 0x38. */ 735 /** 736 * @opcode 0x38 737 */ 571 738 FNIEMOP_DEF(iemOp_cmp_Eb_Gb) 572 739 { … … 576 743 577 744 578 /** Opcode 0x39. */ 745 /** 746 * @opcode 0x39 747 */ 579 748 FNIEMOP_DEF(iemOp_cmp_Ev_Gv) 580 749 { … … 584 753 585 754 586 /** Opcode 0x3a. */ 755 /** 756 * @opcode 0x3a 757 */ 587 758 FNIEMOP_DEF(iemOp_cmp_Gb_Eb) 588 759 { … … 592 763 593 764 594 /** Opcode 0x3b. */ 765 /** 766 * @opcode 0x3b 767 */ 595 768 FNIEMOP_DEF(iemOp_cmp_Gv_Ev) 596 769 { … … 600 773 601 774 602 /** Opcode 0x3c. */ 775 /** 776 * @opcode 0x3c 777 */ 603 778 FNIEMOP_DEF(iemOp_cmp_Al_Ib) 604 779 { … … 608 783 609 784 610 /** Opcode 0x3d. */ 785 /** 786 * @opcode 0x3d 787 */ 611 788 FNIEMOP_DEF(iemOp_cmp_eAX_Iz) 612 789 { … … 616 793 617 794 618 /** Opcode 0x3e. */ 795 /** 796 * @opcode 0x3e 797 */ 619 798 FNIEMOP_DEF(iemOp_seg_DS) 620 799 { … … 628 807 629 808 630 /** Opcode 0x3f. */ 809 /** 810 * @opcode 0x3f 811 */ 631 812 FNIEMOP_STUB(iemOp_aas); 632 813 … … 677 858 678 859 679 /** Opcode 0x40. */ 860 /** 861 * @opcode 0x40 862 */ 680 863 FNIEMOP_DEF(iemOp_inc_eAX) 681 864 { … … 697 880 698 881 699 /** Opcode 0x41. */ 882 /** 883 * @opcode 0x41 884 */ 700 885 FNIEMOP_DEF(iemOp_inc_eCX) 701 886 { … … 718 903 719 904 720 /** Opcode 0x42. */ 905 /** 906 * @opcode 0x42 907 */ 721 908 FNIEMOP_DEF(iemOp_inc_eDX) 722 909 { … … 740 927 741 928 742 /** Opcode 0x43. */ 929 /** 930 * @opcode 0x43 931 */ 743 932 FNIEMOP_DEF(iemOp_inc_eBX) 744 933 { … … 762 951 763 952 764 /** Opcode 0x44. */ 953 /** 954 * @opcode 0x44 955 */ 765 956 FNIEMOP_DEF(iemOp_inc_eSP) 766 957 { … … 783 974 784 975 785 /** Opcode 0x45. */ 976 /** 977 * @opcode 0x45 978 */ 786 979 FNIEMOP_DEF(iemOp_inc_eBP) 787 980 { … … 805 998 806 999 807 /** Opcode 0x46. */ 1000 /** 1001 * @opcode 0x46 1002 */ 808 1003 FNIEMOP_DEF(iemOp_inc_eSI) 809 1004 { … … 827 1022 828 1023 829 /** Opcode 0x47. */ 1024 /** 1025 * @opcode 0x47 1026 */ 830 1027 FNIEMOP_DEF(iemOp_inc_eDI) 831 1028 { … … 850 1047 851 1048 852 /** Opcode 0x48. */ 1049 /** 1050 * @opcode 0x48 1051 */ 853 1052 FNIEMOP_DEF(iemOp_dec_eAX) 854 1053 { … … 871 1070 872 1071 873 /** Opcode 0x49. */ 1072 /** 1073 * @opcode 0x49 1074 */ 874 1075 FNIEMOP_DEF(iemOp_dec_eCX) 875 1076 { … … 893 1094 894 1095 895 /** Opcode 0x4a. */ 1096 /** 1097 * @opcode 0x4a 1098 */ 896 1099 FNIEMOP_DEF(iemOp_dec_eDX) 897 1100 { … … 915 1118 916 1119 917 /** Opcode 0x4b. */ 1120 /** 1121 * @opcode 0x4b 1122 */ 918 1123 FNIEMOP_DEF(iemOp_dec_eBX) 919 1124 { … … 938 1143 939 1144 940 /** Opcode 0x4c. */ 1145 /** 1146 * @opcode 0x4c 1147 */ 941 1148 FNIEMOP_DEF(iemOp_dec_eSP) 942 1149 { … … 960 1167 961 1168 962 /** Opcode 0x4d. */ 1169 /** 1170 * @opcode 0x4d 1171 */ 963 1172 FNIEMOP_DEF(iemOp_dec_eBP) 964 1173 { … … 983 1192 984 1193 985 /** Opcode 0x4e. */ 1194 /** 1195 * @opcode 0x4e 1196 */ 986 1197 FNIEMOP_DEF(iemOp_dec_eSI) 987 1198 { … … 1006 1217 1007 1218 1008 /** Opcode 0x4f. */ 1219 /** 1220 * @opcode 0x4f 1221 */ 1009 1222 FNIEMOP_DEF(iemOp_dec_eDI) 1010 1223 { … … 1077 1290 1078 1291 1079 /** Opcode 0x50. */ 1292 /** 1293 * @opcode 0x50 1294 */ 1080 1295 FNIEMOP_DEF(iemOp_push_eAX) 1081 1296 { … … 1085 1300 1086 1301 1087 /** Opcode 0x51. */ 1302 /** 1303 * @opcode 0x51 1304 */ 1088 1305 FNIEMOP_DEF(iemOp_push_eCX) 1089 1306 { … … 1093 1310 1094 1311 1095 /** Opcode 0x52. */ 1312 /** 1313 * @opcode 0x52 1314 */ 1096 1315 FNIEMOP_DEF(iemOp_push_eDX) 1097 1316 { … … 1101 1320 1102 1321 1103 /** Opcode 0x53. */ 1322 /** 1323 * @opcode 0x53 1324 */ 1104 1325 FNIEMOP_DEF(iemOp_push_eBX) 1105 1326 { … … 1109 1330 1110 1331 1111 /** Opcode 0x54. */ 1332 /** 1333 * @opcode 0x54 1334 */ 1112 1335 FNIEMOP_DEF(iemOp_push_eSP) 1113 1336 { … … 1127 1350 1128 1351 1129 /** Opcode 0x55. */ 1352 /** 1353 * @opcode 0x55 1354 */ 1130 1355 FNIEMOP_DEF(iemOp_push_eBP) 1131 1356 { … … 1135 1360 1136 1361 1137 /** Opcode 0x56. */ 1362 /** 1363 * @opcode 0x56 1364 */ 1138 1365 FNIEMOP_DEF(iemOp_push_eSI) 1139 1366 { … … 1143 1370 1144 1371 1145 /** Opcode 0x57. */ 1372 /** 1373 * @opcode 0x57 1374 */ 1146 1375 FNIEMOP_DEF(iemOp_push_eDI) 1147 1376 { … … 1199 1428 1200 1429 1201 /** Opcode 0x58. */ 1430 /** 1431 * @opcode 0x58 1432 */ 1202 1433 FNIEMOP_DEF(iemOp_pop_eAX) 1203 1434 { … … 1207 1438 1208 1439 1209 /** Opcode 0x59. */ 1440 /** 1441 * @opcode 0x59 1442 */ 1210 1443 FNIEMOP_DEF(iemOp_pop_eCX) 1211 1444 { … … 1215 1448 1216 1449 1217 /** Opcode 0x5a. */ 1450 /** 1451 * @opcode 0x5a 1452 */ 1218 1453 FNIEMOP_DEF(iemOp_pop_eDX) 1219 1454 { … … 1223 1458 1224 1459 1225 /** Opcode 0x5b. */ 1460 /** 1461 * @opcode 0x5b 1462 */ 1226 1463 FNIEMOP_DEF(iemOp_pop_eBX) 1227 1464 { … … 1231 1468 1232 1469 1233 /** Opcode 0x5c. */ 1470 /** 1471 * @opcode 0x5c 1472 */ 1234 1473 FNIEMOP_DEF(iemOp_pop_eSP) 1235 1474 { … … 1280 1519 1281 1520 1282 /** Opcode 0x5d. */ 1521 /** 1522 * @opcode 0x5d 1523 */ 1283 1524 FNIEMOP_DEF(iemOp_pop_eBP) 1284 1525 { … … 1288 1529 1289 1530 1290 /** Opcode 0x5e. */ 1531 /** 1532 * @opcode 0x5e 1533 */ 1291 1534 FNIEMOP_DEF(iemOp_pop_eSI) 1292 1535 { … … 1296 1539 1297 1540 1298 /** Opcode 0x5f. */ 1541 /** 1542 * @opcode 0x5f 1543 */ 1299 1544 FNIEMOP_DEF(iemOp_pop_eDI) 1300 1545 { … … 1304 1549 1305 1550 1306 /** Opcode 0x60. */ 1551 /** 1552 * @opcode 0x60 1553 */ 1307 1554 FNIEMOP_DEF(iemOp_pusha) 1308 1555 { … … 1317 1564 1318 1565 1319 /** Opcode 0x61. */ 1566 /** 1567 * @opcode 0x61 1568 */ 1320 1569 FNIEMOP_DEF(iemOp_popa__mvex) 1321 1570 { … … 1336 1585 1337 1586 1338 /** Opcode 0x62. */ 1587 /** 1588 * @opcode 0x62 1589 * @opmnemonic bound 1590 * @op1 Gv 1591 * @op2 Ma 1592 * @opmincpu 80186 1593 * @ophints harmless invalid_64 1594 */ 1339 1595 FNIEMOP_STUB(iemOp_bound_Gv_Ma__evex); 1340 1596 // IEMOP_HLP_MIN_186(); … … 1392 1648 1393 1649 1394 /** Opcode 0x63. 1650 /** 1651 * @opcode 0x63 1652 * 1395 1653 * @note This is a weird one. It works like a regular move instruction if 1396 1654 * REX.W isn't set, at least according to AMD docs (rev 3.15, 2009-11). … … 1435 1693 1436 1694 1437 /** Opcode 0x64. */ 1695 /** 1696 * @opcode 0x64 1697 * @opmnemonic segfs 1698 * @opmincpu 80386 1699 * @opgroup op_prefixes 1700 */ 1438 1701 FNIEMOP_DEF(iemOp_seg_FS) 1439 1702 { … … 1449 1712 1450 1713 1451 /** Opcode 0x65. */ 1714 /** 1715 * @opcode 0x65 1716 * @opmnemonic seggs 1717 * @opmincpu 80386 1718 * @opgroup op_prefixes 1719 */ 1452 1720 FNIEMOP_DEF(iemOp_seg_GS) 1453 1721 { … … 1463 1731 1464 1732 1465 /** Opcode 0x66. */ 1733 /** 1734 * @opcode 0x66 1735 * @opmnemonic opsize 1736 * @openc prefix 1737 * @opmincpu 80386 1738 * @ophints harmless 1739 * @opgroup op_prefixes 1740 */ 1466 1741 FNIEMOP_DEF(iemOp_op_size) 1467 1742 { … … 1482 1757 1483 1758 1484 /** Opcode 0x67. */ 1759 /** 1760 * @opcode 0x67 1761 * @opmnemonic addrsize 1762 * @openc prefix 1763 * @opmincpu 80386 1764 * @ophints harmless 1765 * @opgroup op_prefixes 1766 */ 1485 1767 FNIEMOP_DEF(iemOp_addr_size) 1486 1768 { … … 1502 1784 1503 1785 1504 /** Opcode 0x68. */ 1786 /** 1787 * @opcode 0x68 1788 */ 1505 1789 FNIEMOP_DEF(iemOp_push_Iz) 1506 1790 { … … 1548 1832 1549 1833 1550 /** Opcode 0x69. */ 1834 /** 1835 * @opcode 0x69 1836 */ 1551 1837 FNIEMOP_DEF(iemOp_imul_Gv_Ev_Iz) 1552 1838 { … … 1709 1995 1710 1996 1711 /** Opcode 0x6a. */ 1997 /** 1998 * @opcode 0x6a 1999 */ 1712 2000 FNIEMOP_DEF(iemOp_push_Ib) 1713 2001 { … … 1737 2025 1738 2026 1739 /** Opcode 0x6b. */ 2027 /** 2028 * @opcode 0x6b 2029 */ 1740 2030 FNIEMOP_DEF(iemOp_imul_Gv_Ev_Ib) 1741 2031 { … … 1892 2182 1893 2183 1894 /** Opcode 0x6c. */ 2184 /** 2185 * @opcode 0x6c 2186 */ 1895 2187 FNIEMOP_DEF(iemOp_insb_Yb_DX) 1896 2188 { … … 1922 2214 1923 2215 1924 /** Opcode 0x6d. */ 2216 /** 2217 * @opcode 0x6d 2218 */ 1925 2219 FNIEMOP_DEF(iemOp_inswd_Yv_DX) 1926 2220 { … … 1984 2278 1985 2279 1986 /** Opcode 0x6e. */ 2280 /** 2281 * @opcode 0x6e 2282 */ 1987 2283 FNIEMOP_DEF(iemOp_outsb_Yb_DX) 1988 2284 { … … 2014 2310 2015 2311 2016 /** Opcode 0x6f. */ 2312 /** 2313 * @opcode 0x6f 2314 */ 2017 2315 FNIEMOP_DEF(iemOp_outswd_Yv_DX) 2018 2316 { … … 2076 2374 2077 2375 2078 /** Opcode 0x70. */ 2376 /** 2377 * @opcode 0x70 2378 */ 2079 2379 FNIEMOP_DEF(iemOp_jo_Jb) 2080 2380 { … … 2095 2395 2096 2396 2097 /** Opcode 0x71. */ 2397 /** 2398 * @opcode 0x71 2399 */ 2098 2400 FNIEMOP_DEF(iemOp_jno_Jb) 2099 2401 { … … 2113 2415 } 2114 2416 2115 /** Opcode 0x72. */ 2417 /** 2418 * @opcode 0x72 2419 */ 2116 2420 FNIEMOP_DEF(iemOp_jc_Jb) 2117 2421 { … … 2132 2436 2133 2437 2134 /** Opcode 0x73. */ 2438 /** 2439 * @opcode 0x73 2440 */ 2135 2441 FNIEMOP_DEF(iemOp_jnc_Jb) 2136 2442 { … … 2151 2457 2152 2458 2153 /** Opcode 0x74. */ 2459 /** 2460 * @opcode 0x74 2461 */ 2154 2462 FNIEMOP_DEF(iemOp_je_Jb) 2155 2463 { … … 2170 2478 2171 2479 2172 /** Opcode 0x75. */ 2480 /** 2481 * @opcode 0x75 2482 */ 2173 2483 FNIEMOP_DEF(iemOp_jne_Jb) 2174 2484 { … … 2189 2499 2190 2500 2191 /** Opcode 0x76. */ 2501 /** 2502 * @opcode 0x76 2503 */ 2192 2504 FNIEMOP_DEF(iemOp_jbe_Jb) 2193 2505 { … … 2208 2520 2209 2521 2210 /** Opcode 0x77. */ 2522 /** 2523 * @opcode 0x77 2524 */ 2211 2525 FNIEMOP_DEF(iemOp_jnbe_Jb) 2212 2526 { … … 2227 2541 2228 2542 2229 /** Opcode 0x78. */ 2543 /** 2544 * @opcode 0x78 2545 */ 2230 2546 FNIEMOP_DEF(iemOp_js_Jb) 2231 2547 { … … 2246 2562 2247 2563 2248 /** Opcode 0x79. */ 2564 /** 2565 * @opcode 0x79 2566 */ 2249 2567 FNIEMOP_DEF(iemOp_jns_Jb) 2250 2568 { … … 2265 2583 2266 2584 2267 /** Opcode 0x7a. */ 2585 /** 2586 * @opcode 0x7a 2587 */ 2268 2588 FNIEMOP_DEF(iemOp_jp_Jb) 2269 2589 { … … 2284 2604 2285 2605 2286 /** Opcode 0x7b. */ 2606 /** 2607 * @opcode 0x7b 2608 */ 2287 2609 FNIEMOP_DEF(iemOp_jnp_Jb) 2288 2610 { … … 2303 2625 2304 2626 2305 /** Opcode 0x7c. */ 2627 /** 2628 * @opcode 0x7c 2629 */ 2306 2630 FNIEMOP_DEF(iemOp_jl_Jb) 2307 2631 { … … 2322 2646 2323 2647 2324 /** Opcode 0x7d. */ 2648 /** 2649 * @opcode 0x7d 2650 */ 2325 2651 FNIEMOP_DEF(iemOp_jnl_Jb) 2326 2652 { … … 2341 2667 2342 2668 2343 /** Opcode 0x7e. */ 2669 /** 2670 * @opcode 0x7e 2671 */ 2344 2672 FNIEMOP_DEF(iemOp_jle_Jb) 2345 2673 { … … 2360 2688 2361 2689 2362 /** Opcode 0x7f. */ 2690 /** 2691 * @opcode 0x7f 2692 */ 2363 2693 FNIEMOP_DEF(iemOp_jnle_Jb) 2364 2694 { … … 2379 2709 2380 2710 2381 /** Opcode 0x80. */ 2711 /** 2712 * @opcode 0x80 2713 */ 2382 2714 FNIEMOP_DEF(iemOp_Grp1_Eb_Ib_80) 2383 2715 { … … 2450 2782 2451 2783 2452 /** Opcode 0x81. */ 2784 /** 2785 * @opcode 0x81 2786 */ 2453 2787 FNIEMOP_DEF(iemOp_Grp1_Ev_Iz) 2454 2788 { … … 2639 2973 2640 2974 2641 /** Opcode 0x82. */ 2975 /** 2976 * @opcode 0x82 2977 * @opmnemonic grp1_82 2978 * @opgroup op_groups 2979 */ 2642 2980 FNIEMOP_DEF(iemOp_Grp1_Eb_Ib_82) 2643 2981 { … … 2647 2985 2648 2986 2649 /** Opcode 0x83. */ 2987 /** 2988 * @opcode 0x83 2989 */ 2650 2990 FNIEMOP_DEF(iemOp_Grp1_Ev_Ib) 2651 2991 { … … 2831 3171 2832 3172 2833 /** Opcode 0x84. */ 3173 /** 3174 * @opcode 0x84 3175 */ 2834 3176 FNIEMOP_DEF(iemOp_test_Eb_Gb) 2835 3177 { … … 2840 3182 2841 3183 2842 /** Opcode 0x85. */ 3184 /** 3185 * @opcode 0x85 3186 */ 2843 3187 FNIEMOP_DEF(iemOp_test_Ev_Gv) 2844 3188 { … … 2849 3193 2850 3194 2851 /** Opcode 0x86. */ 3195 /** 3196 * @opcode 0x86 3197 */ 2852 3198 FNIEMOP_DEF(iemOp_xchg_Eb_Gb) 2853 3199 { … … 2898 3244 2899 3245 2900 /** Opcode 0x87. */ 3246 /** 3247 * @opcode 0x87 3248 */ 2901 3249 FNIEMOP_DEF(iemOp_xchg_Ev_Gv) 2902 3250 { … … 3021 3369 3022 3370 3023 /** Opcode 0x88. */ 3371 /** 3372 * @opcode 0x88 3373 */ 3024 3374 FNIEMOP_DEF(iemOp_mov_Eb_Gb) 3025 3375 { … … 3062 3412 3063 3413 3064 /** Opcode 0x89. */ 3414 /** 3415 * @opcode 0x89 3416 */ 3065 3417 FNIEMOP_DEF(iemOp_mov_Ev_Gv) 3066 3418 { … … 3153 3505 3154 3506 3155 /** Opcode 0x8a. */ 3507 /** 3508 * @opcode 0x8a 3509 */ 3156 3510 FNIEMOP_DEF(iemOp_mov_Gb_Eb) 3157 3511 { … … 3192 3546 3193 3547 3194 /** Opcode 0x8b. */ 3548 /** 3549 * @opcode 0x8b 3550 */ 3195 3551 FNIEMOP_DEF(iemOp_mov_Gv_Ev) 3196 3552 { … … 3283 3639 3284 3640 3285 /** Opcode 0x63. */ 3641 /** 3642 * opcode 0x63 3643 * @todo Table fixme 3644 */ 3286 3645 FNIEMOP_DEF(iemOp_arpl_Ew_Gw_movsx_Gv_Ev) 3287 3646 { … … 3294 3653 3295 3654 3296 /** Opcode 0x8c. */ 3655 /** 3656 * @opcode 0x8c 3657 */ 3297 3658 FNIEMOP_DEF(iemOp_mov_Ev_Sw) 3298 3659 { … … 3371 3732 3372 3733 3373 /** Opcode 0x8d. */ 3734 /** 3735 * @opcode 0x8d 3736 */ 3374 3737 FNIEMOP_DEF(iemOp_lea_Gv_M) 3375 3738 { … … 3419 3782 3420 3783 3421 /** Opcode 0x8e. */ 3784 /** 3785 * @opcode 0x8e 3786 */ 3422 3787 FNIEMOP_DEF(iemOp_mov_Sw_Ev) 3423 3788 { … … 3571 3936 3572 3937 3573 /** Opcode 0x8f. */ 3938 /** 3939 * @opcode 0x8f 3940 */ 3574 3941 FNIEMOP_DEF(iemOp_Grp1A__xop) 3575 3942 { … … 3684 4051 3685 4052 3686 /** Opcode 0x90. */ 4053 /** 4054 * @opcode 0x90 4055 */ 3687 4056 FNIEMOP_DEF(iemOp_nop) 3688 4057 { … … 3705 4074 3706 4075 3707 /** Opcode 0x91. */ 4076 /** 4077 * @opcode 0x91 4078 */ 3708 4079 FNIEMOP_DEF(iemOp_xchg_eCX_eAX) 3709 4080 { … … 3713 4084 3714 4085 3715 /** Opcode 0x92. */ 4086 /** 4087 * @opcode 0x92 4088 */ 3716 4089 FNIEMOP_DEF(iemOp_xchg_eDX_eAX) 3717 4090 { … … 3721 4094 3722 4095 3723 /** Opcode 0x93. */ 4096 /** 4097 * @opcode 0x93 4098 */ 3724 4099 FNIEMOP_DEF(iemOp_xchg_eBX_eAX) 3725 4100 { … … 3729 4104 3730 4105 3731 /** Opcode 0x94. */ 4106 /** 4107 * @opcode 0x94 4108 */ 3732 4109 FNIEMOP_DEF(iemOp_xchg_eSP_eAX) 3733 4110 { … … 3737 4114 3738 4115 3739 /** Opcode 0x95. */ 4116 /** 4117 * @opcode 0x95 4118 */ 3740 4119 FNIEMOP_DEF(iemOp_xchg_eBP_eAX) 3741 4120 { … … 3745 4124 3746 4125 3747 /** Opcode 0x96. */ 4126 /** 4127 * @opcode 0x96 4128 */ 3748 4129 FNIEMOP_DEF(iemOp_xchg_eSI_eAX) 3749 4130 { … … 3753 4134 3754 4135 3755 /** Opcode 0x97. */ 4136 /** 4137 * @opcode 0x97 4138 */ 3756 4139 FNIEMOP_DEF(iemOp_xchg_eDI_eAX) 3757 4140 { … … 3761 4144 3762 4145 3763 /** Opcode 0x98. */ 4146 /** 4147 * @opcode 0x98 4148 */ 3764 4149 FNIEMOP_DEF(iemOp_cbw) 3765 4150 { … … 3808 4193 3809 4194 3810 /** Opcode 0x99. */ 4195 /** 4196 * @opcode 0x99 4197 */ 3811 4198 FNIEMOP_DEF(iemOp_cwd) 3812 4199 { … … 3855 4242 3856 4243 3857 /** Opcode 0x9a. */ 4244 /** 4245 * @opcode 0x9a 4246 */ 3858 4247 FNIEMOP_DEF(iemOp_call_Ap) 3859 4248 { … … 3888 4277 3889 4278 3890 /** Opcode 0x9c. */ 4279 /** 4280 * @opcode 0x9c 4281 */ 3891 4282 FNIEMOP_DEF(iemOp_pushf_Fv) 3892 4283 { … … 3897 4288 3898 4289 3899 /** Opcode 0x9d. */ 4290 /** 4291 * @opcode 0x9d 4292 */ 3900 4293 FNIEMOP_DEF(iemOp_popf_Fv) 3901 4294 { … … 3906 4299 3907 4300 3908 /** Opcode 0x9e. */ 4301 /** 4302 * @opcode 0x9e 4303 */ 3909 4304 FNIEMOP_DEF(iemOp_sahf) 3910 4305 { … … 3930 4325 3931 4326 3932 /** Opcode 0x9f. */ 4327 /** 4328 * @opcode 0x9f 4329 */ 3933 4330 FNIEMOP_DEF(iemOp_lahf) 3934 4331 { … … 3949 4346 3950 4347 /** 3951 * Macro used by iemOp_mov_A l_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL and4348 * Macro used by iemOp_mov_AL_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL and 3952 4349 * iemOp_mov_Ov_rAX to fetch the moffsXX bit of the opcode and fend of lock 3953 4350 * prefixes. Will return on failures. … … 3973 4370 } while (0) 3974 4371 3975 /** Opcode 0xa0. */ 3976 FNIEMOP_DEF(iemOp_mov_Al_Ob) 4372 /** 4373 * @opcode 0xa0 4374 */ 4375 FNIEMOP_DEF(iemOp_mov_AL_Ob) 3977 4376 { 3978 4377 /* … … 3995 4394 3996 4395 3997 /** Opcode 0xa1. */ 4396 /** 4397 * @opcode 0xa1 4398 */ 3998 4399 FNIEMOP_DEF(iemOp_mov_rAX_Ov) 3999 4400 { … … 4042 4443 4043 4444 4044 /** Opcode 0xa2. */ 4445 /** 4446 * @opcode 0xa2 4447 */ 4045 4448 FNIEMOP_DEF(iemOp_mov_Ob_AL) 4046 4449 { … … 4064 4467 4065 4468 4066 /** Opcode 0xa3. */ 4469 /** 4470 * @opcode 0xa3 4471 */ 4067 4472 FNIEMOP_DEF(iemOp_mov_Ov_rAX) 4068 4473 { … … 4128 4533 IEM_MC_END(); 4129 4534 4130 /** Opcode 0xa4. */ 4535 /** 4536 * @opcode 0xa4 4537 */ 4131 4538 FNIEMOP_DEF(iemOp_movsb_Xb_Yb) 4132 4539 { … … 4163 4570 4164 4571 4165 /** Opcode 0xa5. */ 4572 /** 4573 * @opcode 0xa5 4574 */ 4166 4575 FNIEMOP_DEF(iemOp_movswd_Xv_Yv) 4167 4576 { … … 4275 4684 IEM_MC_END(); \ 4276 4685 4277 /** Opcode 0xa6. */ 4686 /** 4687 * @opcode 0xa6 4688 */ 4278 4689 FNIEMOP_DEF(iemOp_cmpsb_Xb_Yb) 4279 4690 { … … 4322 4733 4323 4734 4324 /** Opcode 0xa7. */ 4735 /** 4736 * @opcode 0xa7 4737 */ 4325 4738 FNIEMOP_DEF(iemOp_cmpswd_Xv_Yv) 4326 4739 { … … 4443 4856 #undef IEM_CMPS_CASE 4444 4857 4445 /** Opcode 0xa8. */ 4858 /** 4859 * @opcode 0xa8 4860 */ 4446 4861 FNIEMOP_DEF(iemOp_test_AL_Ib) 4447 4862 { … … 4452 4867 4453 4868 4454 /** Opcode 0xa9. */ 4869 /** 4870 * @opcode 0xa9 4871 */ 4455 4872 FNIEMOP_DEF(iemOp_test_eAX_Iz) 4456 4873 { … … 4477 4894 IEM_MC_END(); \ 4478 4895 4479 /** Opcode 0xaa. */ 4896 /** 4897 * @opcode 0xaa 4898 */ 4480 4899 FNIEMOP_DEF(iemOp_stosb_Yb_AL) 4481 4900 { … … 4512 4931 4513 4932 4514 /** Opcode 0xab. */ 4933 /** 4934 * @opcode 0xab 4935 */ 4515 4936 FNIEMOP_DEF(iemOp_stoswd_Yv_eAX) 4516 4937 { … … 4613 5034 IEM_MC_END(); 4614 5035 4615 /** Opcode 0xac. */ 5036 /** 5037 * @opcode 0xac 5038 */ 4616 5039 FNIEMOP_DEF(iemOp_lodsb_AL_Xb) 4617 5040 { … … 4648 5071 4649 5072 4650 /** Opcode 0xad. */ 5073 /** 5074 * @opcode 0xad 5075 */ 4651 5076 FNIEMOP_DEF(iemOp_lodswd_eAX_Xv) 4652 5077 { … … 4755 5180 IEM_MC_END(); 4756 5181 4757 /** Opcode 0xae. */ 5182 /** 5183 * @opcode 0xae 5184 */ 4758 5185 FNIEMOP_DEF(iemOp_scasb_AL_Xb) 4759 5186 { … … 4801 5228 4802 5229 4803 /** Opcode 0xaf. */ 5230 /** 5231 * @opcode 0xaf 5232 */ 4804 5233 FNIEMOP_DEF(iemOp_scaswd_eAX_Xv) 4805 5234 { … … 4937 5366 4938 5367 4939 /** Opcode 0xb0. */ 5368 /** 5369 * @opcode 0xb0 5370 */ 4940 5371 FNIEMOP_DEF(iemOp_mov_AL_Ib) 4941 5372 { … … 4945 5376 4946 5377 4947 /** Opcode 0xb1. */ 5378 /** 5379 * @opcode 0xb1 5380 */ 4948 5381 FNIEMOP_DEF(iemOp_CL_Ib) 4949 5382 { … … 4953 5386 4954 5387 4955 /** Opcode 0xb2. */ 5388 /** 5389 * @opcode 0xb2 5390 */ 4956 5391 FNIEMOP_DEF(iemOp_DL_Ib) 4957 5392 { … … 4961 5396 4962 5397 4963 /** Opcode 0xb3. */ 5398 /** 5399 * @opcode 0xb3 5400 */ 4964 5401 FNIEMOP_DEF(iemOp_BL_Ib) 4965 5402 { … … 4969 5406 4970 5407 4971 /** Opcode 0xb4. */ 5408 /** 5409 * @opcode 0xb4 5410 */ 4972 5411 FNIEMOP_DEF(iemOp_mov_AH_Ib) 4973 5412 { … … 4977 5416 4978 5417 4979 /** Opcode 0xb5. */ 5418 /** 5419 * @opcode 0xb5 5420 */ 4980 5421 FNIEMOP_DEF(iemOp_CH_Ib) 4981 5422 { … … 4985 5426 4986 5427 4987 /** Opcode 0xb6. */ 5428 /** 5429 * @opcode 0xb6 5430 */ 4988 5431 FNIEMOP_DEF(iemOp_DH_Ib) 4989 5432 { … … 4993 5436 4994 5437 4995 /** Opcode 0xb7. */ 5438 /** 5439 * @opcode 0xb7 5440 */ 4996 5441 FNIEMOP_DEF(iemOp_BH_Ib) 4997 5442 { … … 5051 5496 5052 5497 5053 /** Opcode 0xb8. */ 5498 /** 5499 * @opcode 0xb8 5500 */ 5054 5501 FNIEMOP_DEF(iemOp_eAX_Iv) 5055 5502 { … … 5059 5506 5060 5507 5061 /** Opcode 0xb9. */ 5508 /** 5509 * @opcode 0xb9 5510 */ 5062 5511 FNIEMOP_DEF(iemOp_eCX_Iv) 5063 5512 { … … 5067 5516 5068 5517 5069 /** Opcode 0xba. */ 5518 /** 5519 * @opcode 0xba 5520 */ 5070 5521 FNIEMOP_DEF(iemOp_eDX_Iv) 5071 5522 { … … 5075 5526 5076 5527 5077 /** Opcode 0xbb. */ 5528 /** 5529 * @opcode 0xbb 5530 */ 5078 5531 FNIEMOP_DEF(iemOp_eBX_Iv) 5079 5532 { … … 5083 5536 5084 5537 5085 /** Opcode 0xbc. */ 5538 /** 5539 * @opcode 0xbc 5540 */ 5086 5541 FNIEMOP_DEF(iemOp_eSP_Iv) 5087 5542 { … … 5091 5546 5092 5547 5093 /** Opcode 0xbd. */ 5548 /** 5549 * @opcode 0xbd 5550 */ 5094 5551 FNIEMOP_DEF(iemOp_eBP_Iv) 5095 5552 { … … 5099 5556 5100 5557 5101 /** Opcode 0xbe. */ 5558 /** 5559 * @opcode 0xbe 5560 */ 5102 5561 FNIEMOP_DEF(iemOp_eSI_Iv) 5103 5562 { … … 5107 5566 5108 5567 5109 /** Opcode 0xbf. */ 5568 /** 5569 * @opcode 0xbf 5570 */ 5110 5571 FNIEMOP_DEF(iemOp_eDI_Iv) 5111 5572 { … … 5115 5576 5116 5577 5117 /** Opcode 0xc0. */ 5578 /** 5579 * @opcode 0xc0 5580 */ 5118 5581 FNIEMOP_DEF(iemOp_Grp2_Eb_Ib) 5119 5582 { … … 5176 5639 5177 5640 5178 /** Opcode 0xc1. */ 5641 /** 5642 * @opcode 0xc1 5643 */ 5179 5644 FNIEMOP_DEF(iemOp_Grp2_Ev_Ib) 5180 5645 { … … 5317 5782 5318 5783 5319 /** Opcode 0xc2. */ 5784 /** 5785 * @opcode 0xc2 5786 */ 5320 5787 FNIEMOP_DEF(iemOp_retn_Iw) 5321 5788 { … … 5328 5795 5329 5796 5330 /** Opcode 0xc3. */ 5797 /** 5798 * @opcode 0xc3 5799 */ 5331 5800 FNIEMOP_DEF(iemOp_retn) 5332 5801 { … … 5338 5807 5339 5808 5340 /** Opcode 0xc4. */ 5809 /** 5810 * @opcode 0xc4 5811 */ 5341 5812 FNIEMOP_DEF(iemOp_les_Gv_Mp__vex2) 5342 5813 { … … 5381 5852 5382 5853 5383 /** Opcode 0xc5. */ 5854 /** 5855 * @opcode 0xc5 5856 */ 5384 5857 FNIEMOP_DEF(iemOp_lds_Gv_Mp__vex3) 5385 5858 { … … 5450 5923 5451 5924 5452 /** Opcode 0xc6. */ 5925 /** 5926 * @opcode 0xc6 5927 */ 5453 5928 FNIEMOP_DEF(iemOp_Grp11_Eb_Ib) 5454 5929 { … … 5484 5959 5485 5960 5486 /** Opcode 0xc7. */ 5961 /** 5962 * @opcode 0xc7 5963 */ 5487 5964 FNIEMOP_DEF(iemOp_Grp11_Ev_Iz) 5488 5965 { … … 5573 6050 5574 6051 5575 /** Opcode 0xc8. */ 6052 /** 6053 * @opcode 0xc8 6054 */ 5576 6055 FNIEMOP_DEF(iemOp_enter_Iw_Ib) 5577 6056 { … … 5586 6065 5587 6066 5588 /** Opcode 0xc9. */ 6067 /** 6068 * @opcode 0xc9 6069 */ 5589 6070 FNIEMOP_DEF(iemOp_leave) 5590 6071 { … … 5597 6078 5598 6079 5599 /** Opcode 0xca. */ 6080 /** 6081 * @opcode 0xca 6082 */ 5600 6083 FNIEMOP_DEF(iemOp_retf_Iw) 5601 6084 { … … 5608 6091 5609 6092 5610 /** Opcode 0xcb. */ 6093 /** 6094 * @opcode 0xcb 6095 */ 5611 6096 FNIEMOP_DEF(iemOp_retf) 5612 6097 { … … 5618 6103 5619 6104 5620 /** Opcode 0xcc. */ 5621 FNIEMOP_DEF(iemOp_int_3) 6105 /** 6106 * @opcode 0xcc 6107 */ 6108 FNIEMOP_DEF(iemOp_int3) 5622 6109 { 5623 6110 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); … … 5626 6113 5627 6114 5628 /** Opcode 0xcd. */ 6115 /** 6116 * @opcode 0xcd 6117 */ 5629 6118 FNIEMOP_DEF(iemOp_int_Ib) 5630 6119 { … … 5635 6124 5636 6125 5637 /** Opcode 0xce. */ 6126 /** 6127 * @opcode 0xce 6128 */ 5638 6129 FNIEMOP_DEF(iemOp_into) 5639 6130 { … … 5650 6141 5651 6142 5652 /** Opcode 0xcf. */ 6143 /** 6144 * @opcode 0xcf 6145 */ 5653 6146 FNIEMOP_DEF(iemOp_iret) 5654 6147 { … … 5659 6152 5660 6153 5661 /** Opcode 0xd0. */ 6154 /** 6155 * @opcode 0xd0 6156 */ 5662 6157 FNIEMOP_DEF(iemOp_Grp2_Eb_1) 5663 6158 { … … 5717 6212 5718 6213 5719 /** Opcode 0xd1. */ 6214 /** 6215 * @opcode 0xd1 6216 */ 5720 6217 FNIEMOP_DEF(iemOp_Grp2_Ev_1) 5721 6218 { … … 5850 6347 5851 6348 5852 /** Opcode 0xd2. */ 6349 /** 6350 * @opcode 0xd2 6351 */ 5853 6352 FNIEMOP_DEF(iemOp_Grp2_Eb_CL) 5854 6353 { … … 5909 6408 5910 6409 5911 /** Opcode 0xd3. */ 6410 /** 6411 * @opcode 0xd3 6412 */ 5912 6413 FNIEMOP_DEF(iemOp_Grp2_Ev_CL) 5913 6414 { … … 6047 6548 } 6048 6549 6049 /** Opcode 0xd4. */ 6550 /** 6551 * @opcode 0xd4 6552 */ 6050 6553 FNIEMOP_DEF(iemOp_aam_Ib) 6051 6554 { … … 6060 6563 6061 6564 6062 /** Opcode 0xd5. */ 6565 /** 6566 * @opcode 0xd5 6567 */ 6063 6568 FNIEMOP_DEF(iemOp_aad_Ib) 6064 6569 { … … 6071 6576 6072 6577 6073 /** Opcode 0xd6. */ 6578 /** 6579 * @opcode 0xd6 6580 */ 6074 6581 FNIEMOP_DEF(iemOp_salc) 6075 6582 { … … 6092 6599 6093 6600 6094 /** Opcode 0xd7. */ 6601 /** 6602 * @opcode 0xd7 6603 */ 6095 6604 FNIEMOP_DEF(iemOp_xlat) 6096 6605 { … … 6453 6962 6454 6963 6455 /** Opcode 0xd8. */ 6964 /** 6965 * @opcode 0xd8 6966 */ 6456 6967 FNIEMOP_DEF(iemOp_EscF0) 6457 6968 { … … 7239 7750 7240 7751 7241 /** Opcode 0xd9. */ 7752 /** 7753 * @opcode 0xd9 7754 */ 7242 7755 FNIEMOP_DEF(iemOp_EscF1) 7243 7756 { … … 7589 8102 7590 8103 7591 /** Opcode 0xda. */ 8104 /** 8105 * @opcode 0xda 8106 */ 7592 8107 FNIEMOP_DEF(iemOp_EscF2) 7593 8108 { … … 8049 8564 8050 8565 8051 /** Opcode 0xdb. */ 8566 /** 8567 * @opcode 0xdb 8568 */ 8052 8569 FNIEMOP_DEF(iemOp_EscF3) 8053 8570 { … … 8333 8850 8334 8851 8335 /** Opcode 0xdc. */ 8852 /** 8853 * @opcode 0xdc 8854 */ 8336 8855 FNIEMOP_DEF(iemOp_EscF4) 8337 8856 { … … 8643 9162 8644 9163 8645 /** Opcode 0xdd. */ 9164 /** 9165 * @opcode 0xdd 9166 */ 8646 9167 FNIEMOP_DEF(iemOp_EscF5) 8647 9168 { … … 8890 9411 8891 9412 8892 /** Opcode 0xde. */ 9413 /** 9414 * @opcode 0xde 9415 */ 8893 9416 FNIEMOP_DEF(iemOp_EscF6) 8894 9417 { … … 9205 9728 9206 9729 9207 /** Opcode 0xdf. */ 9730 /** 9731 * @opcode 0xdf 9732 */ 9208 9733 FNIEMOP_DEF(iemOp_EscF7) 9209 9734 { … … 9244 9769 9245 9770 9246 /** Opcode 0xe0. */ 9771 /** 9772 * @opcode 0xe0 9773 */ 9247 9774 FNIEMOP_DEF(iemOp_loopne_Jb) 9248 9775 { … … 9292 9819 9293 9820 9294 /** Opcode 0xe1. */ 9821 /** 9822 * @opcode 0xe1 9823 */ 9295 9824 FNIEMOP_DEF(iemOp_loope_Jb) 9296 9825 { … … 9340 9869 9341 9870 9342 /** Opcode 0xe2. */ 9871 /** 9872 * @opcode 0xe2 9873 */ 9343 9874 FNIEMOP_DEF(iemOp_loop_Jb) 9344 9875 { … … 9415 9946 9416 9947 9417 /** Opcode 0xe3. */ 9948 /** 9949 * @opcode 0xe3 9950 */ 9418 9951 FNIEMOP_DEF(iemOp_jecxz_Jb) 9419 9952 { … … 9500 10033 9501 10034 9502 /** Opcode 0xe8. */ 10035 /** 10036 * @opcode 0xe8 10037 */ 9503 10038 FNIEMOP_DEF(iemOp_call_Jv) 9504 10039 { … … 9530 10065 9531 10066 9532 /** Opcode 0xe9. */ 10067 /** 10068 * @opcode 0xe9 10069 */ 9533 10070 FNIEMOP_DEF(iemOp_jmp_Jv) 9534 10071 { … … 9561 10098 9562 10099 9563 /** Opcode 0xea. */ 10100 /** 10101 * @opcode 0xea 10102 */ 9564 10103 FNIEMOP_DEF(iemOp_jmp_Ap) 9565 10104 { … … 9579 10118 9580 10119 9581 /** Opcode 0xeb. */ 10120 /** 10121 * @opcode 0xeb 10122 */ 9582 10123 FNIEMOP_DEF(iemOp_jmp_Jb) 9583 10124 { … … 9630 10171 9631 10172 9632 /** Opcode 0xf0. */ 10173 /** 10174 * @opcode 0xf0 10175 */ 9633 10176 FNIEMOP_DEF(iemOp_lock) 9634 10177 { … … 9641 10184 9642 10185 9643 /** Opcode 0xf1. */ 9644 FNIEMOP_DEF(iemOp_int_1) 10186 /** 10187 * @opcode 0xf1 10188 */ 10189 FNIEMOP_DEF(iemOp_int1) 9645 10190 { 9646 10191 IEMOP_MNEMONIC(int1, "int1"); /* icebp */ … … 9651 10196 9652 10197 9653 /** Opcode 0xf2. */ 10198 /** 10199 * @opcode 0xf2 10200 */ 9654 10201 FNIEMOP_DEF(iemOp_repne) 9655 10202 { … … 9668 10215 9669 10216 9670 /** Opcode 0xf3. */ 10217 /** 10218 * @opcode 0xf3 10219 */ 9671 10220 FNIEMOP_DEF(iemOp_repe) 9672 10221 { … … 9685 10234 9686 10235 9687 /** Opcode 0xf4. */ 10236 /** 10237 * @opcode 0xf4 10238 */ 9688 10239 FNIEMOP_DEF(iemOp_hlt) 9689 10240 { … … 9693 10244 9694 10245 9695 /** Opcode 0xf5. */ 10246 /** 10247 * @opcode 0xf5 10248 */ 9696 10249 FNIEMOP_DEF(iemOp_cmc) 9697 10250 { … … 10257 10810 } 10258 10811 10259 /** Opcode 0xf6. */ 10812 /** 10813 * @opcode 0xf6 10814 */ 10260 10815 FNIEMOP_DEF(iemOp_Grp3_Eb) 10261 10816 { … … 10295 10850 10296 10851 10297 /** Opcode 0xf7. */ 10852 /** 10853 * @opcode 0xf7 10854 */ 10298 10855 FNIEMOP_DEF(iemOp_Grp3_Ev) 10299 10856 { … … 10333 10890 10334 10891 10335 /** Opcode 0xf8. */ 10892 /** 10893 * @opcode 0xf8 10894 */ 10336 10895 FNIEMOP_DEF(iemOp_clc) 10337 10896 { … … 10346 10905 10347 10906 10348 /** Opcode 0xf9. */ 10907 /** 10908 * @opcode 0xf9 10909 */ 10349 10910 FNIEMOP_DEF(iemOp_stc) 10350 10911 { … … 10359 10920 10360 10921 10361 /** Opcode 0xfa. */ 10922 /** 10923 * @opcode 0xfa 10924 */ 10362 10925 FNIEMOP_DEF(iemOp_cli) 10363 10926 { … … 10376 10939 10377 10940 10378 /** Opcode 0xfc. */ 10941 /** 10942 * @opcode 0xfc 10943 */ 10379 10944 FNIEMOP_DEF(iemOp_cld) 10380 10945 { … … 10389 10954 10390 10955 10391 /** Opcode 0xfd. */ 10956 /** 10957 * @opcode 0xfd 10958 */ 10392 10959 FNIEMOP_DEF(iemOp_std) 10393 10960 { … … 10402 10969 10403 10970 10404 /** Opcode 0xfe. */ 10971 /** 10972 * @opcode 0xfe 10973 */ 10405 10974 FNIEMOP_DEF(iemOp_Grp4) 10406 10975 { … … 10739 11308 10740 11309 10741 /** Opcode 0xff. */ 11310 /** 11311 * @opcode 0xff 11312 */ 10742 11313 FNIEMOP_DEF(iemOp_Grp5) 10743 11314 { … … 10812 11383 /* 0x98 */ iemOp_cbw, iemOp_cwd, iemOp_call_Ap, iemOp_wait, 10813 11384 /* 0x9c */ iemOp_pushf_Fv, iemOp_popf_Fv, iemOp_sahf, iemOp_lahf, 10814 /* 0xa0 */ iemOp_mov_A l_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL, iemOp_mov_Ov_rAX,11385 /* 0xa0 */ iemOp_mov_AL_Ob, iemOp_mov_rAX_Ov, iemOp_mov_Ob_AL, iemOp_mov_Ov_rAX, 10815 11386 /* 0xa4 */ iemOp_movsb_Xb_Yb, iemOp_movswd_Xv_Yv, iemOp_cmpsb_Xb_Yb, iemOp_cmpswd_Xv_Yv, 10816 11387 /* 0xa8 */ iemOp_test_AL_Ib, iemOp_test_eAX_Iz, iemOp_stosb_Yb_AL, iemOp_stoswd_Yv_eAX, … … 10823 11394 /* 0xc4 */ iemOp_les_Gv_Mp__vex2, iemOp_lds_Gv_Mp__vex3, iemOp_Grp11_Eb_Ib, iemOp_Grp11_Ev_Iz, 10824 11395 /* 0xc8 */ iemOp_enter_Iw_Ib, iemOp_leave, iemOp_retf_Iw, iemOp_retf, 10825 /* 0xcc */ iemOp_int _3,iemOp_int_Ib, iemOp_into, iemOp_iret,11396 /* 0xcc */ iemOp_int3, iemOp_int_Ib, iemOp_into, iemOp_iret, 10826 11397 /* 0xd0 */ iemOp_Grp2_Eb_1, iemOp_Grp2_Ev_1, iemOp_Grp2_Eb_CL, iemOp_Grp2_Ev_CL, 10827 11398 /* 0xd4 */ iemOp_aam_Ib, iemOp_aad_Ib, iemOp_salc, iemOp_xlat, … … 10832 11403 /* 0xe8 */ iemOp_call_Jv, iemOp_jmp_Jv, iemOp_jmp_Ap, iemOp_jmp_Jb, 10833 11404 /* 0xec */ iemOp_in_AL_DX, iemOp_eAX_DX, iemOp_out_DX_AL, iemOp_out_DX_eAX, 10834 /* 0xf0 */ iemOp_lock, iemOp_int _1,iemOp_repne, iemOp_repe,11405 /* 0xf0 */ iemOp_lock, iemOp_int1, iemOp_repne, iemOp_repe, 10835 11406 /* 0xf4 */ iemOp_hlt, iemOp_cmc, iemOp_Grp3_Eb, iemOp_Grp3_Ev, 10836 11407 /* 0xf8 */ iemOp_clc, iemOp_stc, iemOp_cli, iemOp_sti, -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r65869 r65876 74 74 }; 75 75 76 ## \@op[1-4] locations 77 g_kdOpLocations = { 78 'reg': [], ## modrm.reg 79 'rm': [], ## modrm.rm 80 'imm': [], ## immediate instruction data 81 'vvvv': [], ## VEX.vvvv 82 83 # fixed registers. 84 'AL': [], 85 'rAX': [], 86 'rSI': [], 87 'rDI': [], 88 'rFLAGS': [], 89 'CS': [], 90 'DS': [], 91 'ES': [], 92 'FS': [], 93 'GS': [], 94 'SS': [], 95 }; 96 97 ## \@op[1-4] types 98 ## 99 ## First value entry is the normal IDX_ParseXXX handler (IDX_UseModRM == IDX_ParseModRM). 100 ## Second value entry is the location (g_kdOpLocations). 101 ## Third value entry is disassembler format string version of the type. 102 ## 103 ## Note! See the A.2.1 in SDM vol 2 for the type names. 104 g_kdOpTypes = { 105 # Fixed addresses 106 'Ap': ( 'IDX_ParseImmAddrF', 'imm', '%Ap', ), 107 108 # ModR/M.rm 109 'Eb': ( 'IDX_UseModRM', 'rm', '%Eb', ), 110 'Ew': ( 'IDX_UseModRM', 'rm', '%Ew', ), 111 'Ev': ( 'IDX_UseModRM', 'rm', '%Ev', ), 112 113 # ModR/M.rm - memory only. 114 'Ma': ( 'IDX_UseModRM', 'rm', '%Ma', ), ##< Only used by BOUND. 115 116 # ModR/M.reg 117 'Gb': ( 'IDX_UseModRM', 'reg', '%Gb', ), 118 'Gw': ( 'IDX_UseModRM', 'reg', '%Gw', ), 119 'Gv': ( 'IDX_UseModRM', 'reg', '%Gv', ), 120 121 # Immediate values. 122 'Ib': ( 'IDX_ParseImmByte', 'imm', '%Ib', ), ##< NB! Could be IDX_ParseImmByteSX for some instructions. 123 'Iw': ( 'IDX_ParseImmUshort', 'imm', '%Iw', ), 124 'Id': ( 'IDX_ParseImmUlong', 'imm', '%Id', ), 125 'Iq': ( 'IDX_ParseImmQword', 'imm', '%Iq', ), 126 'Iv': ( 'IDX_ParseImmV', 'imm', '%Iv', ), ##< o16: word, o32: dword, o64: qword 127 'Iz': ( 'IDX_ParseImmZ', 'imm', '%Iz', ), ##< o16: word, o32|o64:dword 128 129 # Address operands (no ModR/M). 130 'Ob': ( 'IDX_ParseImmAddr', 'imm', '%Ob', ), 131 'Ov': ( 'IDX_ParseImmAddr', 'imm', '%Ov', ), 132 133 # Relative jump targets 134 'Jb': ( 'IDX_ParseImmBRel', 'imm', '%Jb', ), 135 'Jv': ( 'IDX_ParseImmVRel', 'imm', '%Jv', ), 136 137 # DS:rSI 138 'Xb': ( 'IDX_ParseXb', 'rSI', '%eSI', ), 139 'Xv': ( 'IDX_ParseXv', 'rSI', '%eSI', ), 140 # ES:rDI 141 'Yb': ( 'IDX_ParseYb', 'rDI', '%eDI', ), 142 'Yv': ( 'IDX_ParseYv', 'rDI', '%eDI', ), 143 144 'Fv': ( 'IDX_ParseFixedReg', 'rFLAGS', '%Fv', ), 145 146 # Fixed registers. 147 'AL': ( 'IDX_ParseFixedReg', 'AL', 'al' ), 148 'rAX': ( 'IDX_ParseFixedReg', 'rAX', '%eAX', ), 149 'CS': ( 'IDX_ParseFixedReg', 'CS', 'cs' ), # 8086: push CS 150 'DS': ( 'IDX_ParseFixedReg', 'DS', 'ds' ), 151 'ES': ( 'IDX_ParseFixedReg', 'ES', 'es' ), 152 'FS': ( 'IDX_ParseFixedReg', 'FS', 'fs' ), 153 'GS': ( 'IDX_ParseFixedReg', 'GS', 'gs' ), 154 'SS': ( 'IDX_ParseFixedReg', 'SS', 'ss' ), 155 }; 156 157 # IDX_ParseFixedReg 158 # IDX_ParseVexDest 159 160 161 ## IEMFORM_XXX mappings. 162 g_kdIemForms = { # sEncoding, [sWhere,] 163 'RM': ( 'ModR/M', [ 'reg', 'rm' ], ), 164 'RM_REG': ( 'ModR/M', [ 'reg', 'rm' ], ), 165 'RM_MEM': ( 'ModR/M', [ 'reg', 'rm' ], ), 166 'MR': ( 'ModR/M', [ 'rm', 'reg' ], ), 167 'MR_REG': ( 'ModR/M', [ 'rm', 'reg' ], ), 168 'MR_MEM': ( 'ModR/M', [ 'rm', 'reg' ], ), 169 'M': ( 'ModR/M', [ 'rm', ], ), 170 'M_REG': ( 'ModR/M', [ 'rm', ], ), 171 'M_MEM': ( 'ModR/M', [ 'rm', ], ), 172 'R': ( 'ModR/M', [ 'reg', ], ), 173 'RVM': ( 'ModR/M+VEX', [ 'reg', 'vvvv', 'rm'], ), 174 'MVR': ( 'ModR/M+VEX', [ 'rm', 'vvvv', 'reg'], ), 175 'FIXED': ( 'fixed', None, ) 176 }; 177 178 ## \@oppfx values. 179 g_kdPrefixes = { 180 '0x66': [], 181 '0xf3': [], 182 '0xf2': [], 183 }; 184 185 ## Special \@opcode tag values. 186 g_kdSpecialOpcodes = { 187 '/reg': [], 188 'mr/reg': [], 189 '11 /reg': [], 190 '!11 /reg': [], 191 '11 mr/reg': [], 192 '!11 mr/reg': [], 193 }; 194 195 ## Valid values for \@openc 196 g_kdEncodings = { 197 'ModR/M': [], ##< ModR/M 198 'fixed': [], ##< Fixed encoding (address, registers, etc). 199 'prefix': [], ##< Prefix 200 }; 201 202 ## \@opunused, \@opinvalid, \@opinvlstyle 203 g_kdInvalidStyles = { 204 'immediate': [], ##< CPU stops decoding immediately after the opcode. 205 'intel-modrm': [], ##< Intel decodes ModR/M. 206 'intel-modrm-imm8': [], ##< Intel decodes ModR/M and an 8-byte immediate. 207 'intel-opcode-modrm': [], ##< Intel decodes another opcode byte followed by ModR/M. (Unused extension tables.) 208 'intel-opcode-modrm-imm8': [], ##< Intel decodes another opcode byte followed by ModR/M and an 8-byte immediate. 209 }; 210 211 g_kdCpuNames = { 212 '8086': (), 213 '80186': (), 214 '80286': (), 215 '80386': (), 216 '80486': (), 217 }; 218 219 ## \@opcpuid 220 g_kdCpuIdFlags = { 221 'vme': 'X86_CPUID_FEATURE_EDX_VME', 222 'tsc': 'X86_CPUID_FEATURE_EDX_TSC', 223 'msr': 'X86_CPUID_FEATURE_EDX_MSR', 224 'cx8': 'X86_CPUID_FEATURE_EDX_CX8', 225 'sep': 'X86_CPUID_FEATURE_EDX_SEP', 226 'cmov': 'X86_CPUID_FEATURE_EDX_CMOV', 227 'clfsh': 'X86_CPUID_FEATURE_EDX_CLFSH', 228 'mmx': 'X86_CPUID_FEATURE_EDX_MMX', 229 'fxsr': 'X86_CPUID_FEATURE_EDX_FXSR', 230 'sse': 'X86_CPUID_FEATURE_EDX_SSE', 231 'sse2': 'X86_CPUID_FEATURE_EDX_SSE2', 232 'sse3': 'X86_CPUID_FEATURE_ECX_SSE3', 233 'pclmul': 'X86_CPUID_FEATURE_ECX_DTES64', 234 'monitor': 'X86_CPUID_FEATURE_ECX_CPLDS', 235 'vmx': 'X86_CPUID_FEATURE_ECX_VMX', 236 'smx': 'X86_CPUID_FEATURE_ECX_TM2', 237 'ssse3': 'X86_CPUID_FEATURE_ECX_SSSE3', 238 'fma': 'X86_CPUID_FEATURE_ECX_FMA', 239 'cx16': 'X86_CPUID_FEATURE_ECX_CX16', 240 'pcid': 'X86_CPUID_FEATURE_ECX_PCID', 241 'sse41': 'X86_CPUID_FEATURE_ECX_SSE4_1', 242 'sse42': 'X86_CPUID_FEATURE_ECX_SSE4_2', 243 'movbe': 'X86_CPUID_FEATURE_ECX_MOVBE', 244 'popcnt': 'X86_CPUID_FEATURE_ECX_POPCNT', 245 'aes': 'X86_CPUID_FEATURE_ECX_AES', 246 'xsave': 'X86_CPUID_FEATURE_ECX_XSAVE', 247 'avx': 'X86_CPUID_FEATURE_ECX_AVX', 248 'f16c': 'X86_CPUID_FEATURE_ECX_F16C', 249 'rdrand': 'X86_CPUID_FEATURE_ECX_RDRAND', 250 251 'axmmx': 'X86_CPUID_AMD_FEATURE_EDX_AXMMX', 252 '3dnowext': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX', 253 '3dnow': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW', 254 'svm': 'X86_CPUID_AMD_FEATURE_ECX_SVM', 255 'cr8l': 'X86_CPUID_AMD_FEATURE_ECX_CR8L', 256 'abm': 'X86_CPUID_AMD_FEATURE_ECX_ABM', 257 'sse4a': 'X86_CPUID_AMD_FEATURE_ECX_SSE4A', 258 '3dnowprf': 'X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF', 259 'xop': 'X86_CPUID_AMD_FEATURE_ECX_XOP', 260 'fma4': 'X86_CPUID_AMD_FEATURE_ECX_FMA4', 261 }; 262 263 ## \@ophints values. 264 g_kdHints = { 265 'invalid': 'DISOPTYPE_INVALID', ##< 266 'harmless': 'DISOPTYPE_HARMLESS', ##< 267 'controlflow': 'DISOPTYPE_CONTROLFLOW', ##< 268 'potentially_dangerous': 'DISOPTYPE_POTENTIALLY_DANGEROUS', ##< 269 'dangerous': 'DISOPTYPE_DANGEROUS', ##< 270 'portio': 'DISOPTYPE_PORTIO', ##< 271 'privileged': 'DISOPTYPE_PRIVILEGED', ##< 272 'privileged_notrap': 'DISOPTYPE_PRIVILEGED_NOTRAP', ##< 273 'uncond_controlflow': 'DISOPTYPE_UNCOND_CONTROLFLOW', ##< 274 'relative_controlflow': 'DISOPTYPE_RELATIVE_CONTROLFLOW', ##< 275 'cond_controlflow': 'DISOPTYPE_COND_CONTROLFLOW', ##< 276 'interrupt': 'DISOPTYPE_INTERRUPT', ##< 277 'illegal': 'DISOPTYPE_ILLEGAL', ##< 278 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. */ 279 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. */ 280 'inhibit_irqs': 'DISOPTYPE_INHIBIT_IRQS', ##< Will or can inhibit irqs (sti, pop ss, mov ss) */ 281 'portio_read': 'DISOPTYPE_PORTIO_READ', ##< 282 'portio_write': 'DISOPTYPE_PORTIO_WRITE', ##< 283 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode */ 284 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode */ 285 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size */ 286 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes */ 287 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte */ 288 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b */ 289 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */ 290 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */ 291 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */ 292 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! */ 293 'ignores_op_size': '', ##< Ignores both operand size prefixes. 294 }; 295 76 296 77 297 def _isValidOpcodeByte(sOpcode): … … 197 417 if oExisting is None: 198 418 aoTable[idxOpcode] = oInstr; 199 elif not isinstance(o Instance, list):200 aoTable[idxOpcode] = list( oExisting, oInstr);419 elif not isinstance(oExisting, list): 420 aoTable[idxOpcode] = list([oExisting, oInstr]); 201 421 else: 202 422 oExisting.append(oInstr); … … 606 826 """ 607 827 608 ## \@op[1-4]609 kdLocations = {610 'reg': [], ## modrm.reg611 'rm': [], ## modrm.rm612 };613 614 ## \@op[1-4]615 ## First value entry is the normal IDX_ParseXXX handler (IDX_UseModRM == IDX_ParseModRM).616 ## Note! See the A.2.1 in SDM vol 2 for the type names.617 kdTypes = {618 # Fixed addresses619 'Ap': ( 'IDX_ParseImmAddrF', ),620 621 # ModR/M.rm622 'Eb': ( 'IDX_UseModRM', ),623 'Ev': ( 'IDX_UseModRM', ),624 625 # ModR/M.reg626 'Gb': ( 'IDX_UseModRM', ),627 'Gv': ( 'IDX_UseModRM', ),628 629 # Immediate values.630 'Ib': ( 'IDX_ParseImmByte', ), ##< NB! Could be IDX_ParseImmByteSX for some instructions.631 'Iw': ( 'IDX_ParseImmUshort', ),632 'Id': ( 'IDX_ParseImmUlong', ),633 'Iq': ( 'IDX_ParseImmQword', ),634 'Iv': ( 'IDX_ParseImmV', ), ##< o16: word, o32: dword, o64: qword635 'Iz': ( 'IDX_ParseImmZ', ), ##< o16: word, o32|o64:dword636 637 # Address operands (no ModR/M).638 'Ob': ( 'IDX_ParseImmAddr', ),639 'Ov': ( 'IDX_ParseImmAddr', ),640 641 # Relative jump targets642 'Jb': ( 'IDX_ParseImmBRel', ),643 'Jv': ( 'IDX_ParseImmVRel', ),644 645 # DS:rSI646 'Xb': ( 'IDX_ParseXb', ),647 'Xv': ( 'IDX_ParseXv', ),648 # ES:rDI649 'Yb': ( 'IDX_ParseYb', ),650 'Yv': ( 'IDX_ParseYv', ),651 652 };653 654 # IDX_ParseFixedReg655 # IDX_ParseVexDest656 657 828 def __init__(self, sWhere, sType): 658 assert sWhere in self.kdLocations;659 assert sType in self.kdTypes;660 self.sWhere = sWhere; ##< kdLocations661 self.sType = sType; ##< kdTypes829 assert sWhere in g_kdOpLocations, sWhere; 830 assert sType in g_kdOpTypes, sType; 831 self.sWhere = sWhere; ##< g_kdOpLocations 832 self.sType = sType; ##< g_kdOpTypes 662 833 663 834 def usesModRM(self): 664 835 """ Returns True if using some form of ModR/M encoding. """ 665 return self.sType[0] in ['E', 'G' ];836 return self.sType[0] in ['E', 'G', 'M']; 666 837 667 838 … … 693 864 self.asReqFeatures = []; ##< Which features are required to be enabled to run this instruction. 694 865 self.aoTests = []; # type: list(InstructionTest) 695 self.oCpus = None; ##< Some CPU restriction expression... 866 self.sMinCpu = None; ##< Indicates the minimum CPU required for the instruction. Not set when oCpuExpr is. 867 self.oCpuExpr = None; ##< Some CPU restriction expression... 696 868 self.sGroup = None; 697 869 self.fUnused = False; ##< Unused instruction. … … 714 886 self.iLineCompleted = None; 715 887 self.cOpTags = 0; 888 self.iLineFnIemOpMacro = -1; 889 self.iLineMnemonicMacro = -1; 716 890 ## @} 717 891 … … 723 897 self.sRawOldOpcodes = None; 724 898 ## @} 899 900 def toString(self, fRepr = False): 901 """ Turn object into a string. """ 902 aasFields = []; 903 904 aasFields.append(['opcode', self.sOpcode]); 905 aasFields.append(['mnemonic', self.sMnemonic]); 906 for iOperand, oOperand in enumerate(self.aoOperands): 907 aasFields.append(['op%u' % (iOperand + 1,), '%s:%s' % (oOperand.sWhere, oOperand.sType,)]); 908 if self.aoMaps: aasFields.append(['maps', ','.join([oMap.sName for oMap in self.aoMaps])]); 909 aasFields.append(['encoding', self.sEncoding]); 910 if self.dHints: aasFields.append(['hints', ','.join(self.dHints.keys())]); 911 aasFields.append(['disenum', self.sDisEnum]); 912 if self.asCpuIds: aasFields.append(['cpuid', ','.join(self.asCpuIds)]); 913 aasFields.append(['group', self.sGroup]); 914 if self.fUnused: aasFields.append(['unused', 'True']); 915 if self.fInvalid: aasFields.append(['invalid', 'True']); 916 aasFields.append(['invlstyle', self.sInvalidStyle]); 917 aasFields.append(['fltest', self.asFlTest]); 918 aasFields.append(['flmodify', self.asFlModify]); 919 aasFields.append(['flundef', self.asFlUndefined]); 920 aasFields.append(['flset', self.asFlSet]); 921 aasFields.append(['flclear', self.asFlClear]); 922 aasFields.append(['mincpu', self.sMinCpu]); 923 aasFields.append(['stats', self.sStats]); 924 aasFields.append(['sFunction', self.sFunction]); 925 if self.fStub: aasFields.append(['fStub', 'True']); 926 if self.fUdStub: aasFields.append(['fUdStub', 'True']); 927 if self.cOpTags: aasFields.append(['optags', str(self.cOpTags)]); 928 if self.iLineFnIemOpMacro != -1: aasFields.append(['FNIEMOP_XXX', str(self.iLineFnIemOpMacro)]); 929 if self.iLineMnemonicMacro != -1: aasFields.append(['IEMOP_MNEMMONICn', str(self.iLineMnemonicMacro)]); 930 931 sRet = '<' if fRepr else ''; 932 for sField, sValue in aasFields: 933 if sValue != None: 934 if len(sRet) > 1: 935 sRet += '; '; 936 sRet += '%s=%s' % (sField, sValue,); 937 if fRepr: 938 sRet += '>'; 939 940 return sRet; 941 942 def __str__(self): 943 """ Provide string represenation. """ 944 return self.toString(False); 945 946 def __repr__(self): 947 """ Provide unambigious string representation. """ 948 return self.toString(True); 725 949 726 950 def getOpcodeByte(self): … … 835 1059 self.sComment = ''; 836 1060 self.iCommentLine = 0; 837 self.a sCurInstr= [];1061 self.aoCurInstrs = []; 838 1062 839 1063 assert sDefaultMap in g_dInstructionMaps; … … 871 1095 '@ophints': self.parseTagOpHints, 872 1096 '@opdisenum': self.parseTagOpDisEnum, 1097 '@opmincpu': self.parseTagOpMinCpu, 873 1098 '@opcpuid': self.parseTagOpCpuId, 874 1099 '@opgroup': self.parseTagOpGroup, … … 934 1159 oInstr = Instruction(self.sSrcFile, self.iLine if iLine is None else iLine); 935 1160 g_aoAllInstructions.append(oInstr); 936 self.a sCurInstr.append(oInstr);1161 self.aoCurInstrs.append(oInstr); 937 1162 return oInstr; 1163 1164 def deriveMnemonicAndOperandsFromStats(self, oInstr, sStats): 1165 """ 1166 Derives the mnemonic and operands from a IEM stats base name like string. 1167 """ 1168 if oInstr.sMnemonic is None: 1169 asWords = sStats.split('_'); 1170 oInstr.sMnemonic = asWords[0].lower(); 1171 if len(asWords) > 1 and len(oInstr.aoOperands) == 0: 1172 for sType in asWords[1:]: 1173 if sType in g_kdOpTypes: 1174 oInstr.aoOperands.append(Operand(g_kdOpTypes[sType][1], sType)); 1175 else: 1176 #return self.error('unknown operand type: %s (instruction: %s)' % (sType, oInstr)) 1177 return False; 1178 return True; 938 1179 939 1180 def doneInstructionOne(self, oInstr, iLine): … … 965 1206 # Common defaults. 966 1207 # 1208 1209 # Guess mnemonic and operands from stats if the former is missing. 1210 if oInstr.sMnemonic is None: 1211 if oInstr.sStats is not None: 1212 self.deriveMnemonicAndOperandsFromStats(oInstr, oInstr.sStats); 1213 elif oInstr.sFunction is not None: 1214 self.deriveMnemonicAndOperandsFromStats(oInstr, oInstr.sFunction.replace('iemOp_', '')); 1215 1216 # Derive the disassembler op enum constant from the mnemonic. 967 1217 if oInstr.sDisEnum is None and oInstr.sMnemonic is not None: 968 1218 oInstr.sDisEnum = 'OP_' + oInstr.sMnemonic.upper(); 969 1219 1220 # Derive the IEM statistics base name from mnemonic and operand types. 970 1221 if oInstr.sStats is None: 971 1222 if oInstr.sFunction is not None: … … 977 1228 oInstr.sStats += '_' + oOperand.sType; 978 1229 1230 # Derive the IEM function name from mnemonic and operand types. 979 1231 if oInstr.sFunction is None: 980 1232 if oInstr.sMnemonic is not None: … … 986 1238 oInstr.sFunction = 'iemOp_' + oInstr.sStats; 987 1239 1240 # Derive encoding from operands. 1241 if oInstr.sEncoding is None: 1242 if len(oInstr.aoOperands) == 0: 1243 oInstr.sEncoding = 'fixed'; 1244 elif oInstr.aoOperands[0].usesModRM(): 1245 if len(oInstr.aoOperands) >= 2 and oInstr.aoOperands[1].sWhere == 'vvvv': 1246 oInstr.sEncoding = 'ModR/M+VEX'; 1247 else: 1248 oInstr.sEncoding = 'ModR/M'; 1249 988 1250 # 989 1251 # Apply default map and then add the instruction to all it's groups. … … 1001 1263 Done with current instruction. 1002 1264 """ 1003 for oInstr in self.a sCurInstr:1265 for oInstr in self.aoCurInstrs: 1004 1266 self.doneInstructionOne(oInstr, self.iLine if iLineInComment is None else self.iCommentLine + iLineInComment); 1005 1267 if oInstr.fStub: 1006 1268 self.cTotalStubs += 1; 1007 1269 1008 self.cTotalInstr += len(self.a sCurInstr);1270 self.cTotalInstr += len(self.aoCurInstrs); 1009 1271 1010 1272 self.sComment = ''; 1011 self.a sCurInstr= [];1273 self.aoCurInstrs = []; 1012 1274 return True; 1013 1275 … … 1017 1279 is False, only None values and empty strings are replaced. 1018 1280 """ 1019 for oInstr in self.a sCurInstr:1281 for oInstr in self.aoCurInstrs: 1020 1282 if fOverwrite is not True: 1021 1283 oOldValue = getattr(oInstr, sAttrib); … … 1029 1291 If fOverwrite is False, only None values and empty strings are replaced. 1030 1292 """ 1031 for oInstr in self.a sCurInstr:1293 for oInstr in self.aoCurInstrs: 1032 1294 aoArray = getattr(oInstr, sAttrib); 1033 1295 while len(aoArray) <= iEntry: … … 1054 1316 def ensureInstructionForOpTag(self, iTagLine): 1055 1317 """ Ensure there is an instruction for the op-tag being parsed. """ 1056 if len(self.a sCurInstr) == 0:1318 if len(self.aoCurInstrs) == 0: 1057 1319 self.addInstruction(self.iCommentLine + iTagLine); 1058 for oInstr in self.a sCurInstr:1320 for oInstr in self.aoCurInstrs: 1059 1321 oInstr.cOpTags += 1; 1060 1322 if oInstr.cOpTags == 1: 1061 1323 self.cTotalTagged += 1; 1062 return self.a sCurInstr[-1];1324 return self.aoCurInstrs[-1]; 1063 1325 1064 1326 @staticmethod … … 1168 1430 """ 1169 1431 Tags: \@op1, \@op2, \@op3, \@op4 1170 Value: where:type1432 Value: [where:]type 1171 1433 1172 1434 The 'where' value indicates where the operand is found, like the 'reg' … … 1186 1448 sFlattened = self.flattenAllSections(aasSections); 1187 1449 asSplit = sFlattened.split(':'); 1188 if len(asSplit) != 2: 1189 return self.errorComment(iTagLine, 'expected %s value on format "<where>:<type>" not "%s"' % (sTag, sFlattened,)); 1190 1191 (sWhere, sType) = asSplit; 1192 if sWhere not in Operand.kdLocations: 1450 if len(asSplit) == 1: 1451 sType = asSplit[0]; 1452 sWhere = None; 1453 elif len(asSplit) == 2: 1454 (sWhere, sType) = asSplit; 1455 else: 1456 return self.errorComment(iTagLine, 'expected %s value on format "[<where>:]<type>" not "%s"' % (sTag, sFlattened,)); 1457 1458 if sType not in g_kdOpTypes: 1193 1459 return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s' 1194 % (sTag, sWhere, ', '.join(Operand.kdLocations.keys()),), iTagLine); 1195 1196 if sType not in Operand.kdTypes: 1460 % (sTag, sType, ', '.join(g_kdOpTypes.keys()),)); 1461 if sWhere is None: 1462 sWhere = g_kdOpTypes[sType][1]; 1463 elif sWhere not in g_kdOpLocations: 1197 1464 return self.errorComment(iTagLine, '%s: invalid where value "%s", valid: %s' 1198 % (sTag, s Type, ', '.join(Operand.kdTypes.keys()),));1465 % (sTag, sWhere, ', '.join(g_kdOpLocations.keys()),), iTagLine); 1199 1466 1200 1467 # Insert the operand, refusing to overwrite an existing one. … … 1245 1512 return True; 1246 1513 1247 ## \@oppfx values.1248 kdPrefixes = {1249 '0x66': [],1250 '0xf3': [],1251 '0xf2': [],1252 };1253 1254 1514 def parseTagOpPfx(self, sTag, aasSections, iTagLine, iEndLine): 1255 1515 """ … … 1277 1537 return self.errorComment(iTagLine, '%s: invalid prefix: %s' % (sTag, sPrefix,)); 1278 1538 1279 if sPrefix is not None and sPrefix not in self.kdPrefixes:1280 return self.errorComment(iTagLine, '%s: invalid prefix: %s (valid %s)' % (sTag, sPrefix, self.kdPrefixes,));1539 if sPrefix is not None and sPrefix not in g_kdPrefixes: 1540 return self.errorComment(iTagLine, '%s: invalid prefix: %s (valid %s)' % (sTag, sPrefix, g_kdPrefixes,)); 1281 1541 1282 1542 # Set it. … … 1288 1548 return True; 1289 1549 1290 ## Special \@opcode tag values.1291 kdSpecialOpcodes = {1292 '/reg': [],1293 'mr/reg': [],1294 '11 /reg': [],1295 '!11 /reg': [],1296 '11 mr/reg': [],1297 '!11 mr/reg': [],1298 };1299 1300 1550 def parseTagOpcode(self, sTag, aasSections, iTagLine, iEndLine): 1301 1551 """ … … 1309 1559 # Flatten and validate the value. 1310 1560 sOpcode = self.flattenAllSections(aasSections); 1311 if sOpcode in self.kdSpecialOpcodes:1561 if sOpcode in g_kdSpecialOpcodes: 1312 1562 pass; 1313 1563 elif not _isValidOpcodeByte(sOpcode): … … 1322 1572 return True; 1323 1573 1324 ## Valid values for \@openc1325 kdEncodings = {1326 'ModR/M': [], ##< ModR/M1327 'prefix': [], ##< Prefix1328 };1329 1330 1574 def parseTagOpEnc(self, sTag, aasSections, iTagLine, iEndLine): 1331 1575 """ … … 1339 1583 # Flatten and validate the value. 1340 1584 sEncoding = self.flattenAllSections(aasSections); 1341 if sEncoding in self.kdEncodings:1585 if sEncoding in g_kdEncodings: 1342 1586 pass; 1343 1587 elif not _isValidOpcodeByte(sEncoding): … … 1441 1685 return True; 1442 1686 1443 ## \@ophints values.1444 kdHints = {1445 'invalid': 'DISOPTYPE_INVALID', ##<1446 'harmless': 'DISOPTYPE_HARMLESS', ##<1447 'controlflow': 'DISOPTYPE_CONTROLFLOW', ##<1448 'potentially_dangerous': 'DISOPTYPE_POTENTIALLY_DANGEROUS', ##<1449 'dangerous': 'DISOPTYPE_DANGEROUS', ##<1450 'portio': 'DISOPTYPE_PORTIO', ##<1451 'privileged': 'DISOPTYPE_PRIVILEGED', ##<1452 'privileged_notrap': 'DISOPTYPE_PRIVILEGED_NOTRAP', ##<1453 'uncond_controlflow': 'DISOPTYPE_UNCOND_CONTROLFLOW', ##<1454 'relative_controlflow': 'DISOPTYPE_RELATIVE_CONTROLFLOW', ##<1455 'cond_controlflow': 'DISOPTYPE_COND_CONTROLFLOW', ##<1456 'interrupt': 'DISOPTYPE_INTERRUPT', ##<1457 'illegal': 'DISOPTYPE_ILLEGAL', ##<1458 'rrm_dangerous': 'DISOPTYPE_RRM_DANGEROUS', ##< Some additional dangerous ones when recompiling raw r0. */1459 'rrm_dangerous_16': 'DISOPTYPE_RRM_DANGEROUS_16', ##< Some additional dangerous ones when recompiling 16-bit raw r0. */1460 'inhibit_irqs': 'DISOPTYPE_INHIBIT_IRQS', ##< Will or can inhibit irqs (sti, pop ss, mov ss) */1461 'portio_read': 'DISOPTYPE_PORTIO_READ', ##<1462 'portio_write': 'DISOPTYPE_PORTIO_WRITE', ##<1463 'invalid_64': 'DISOPTYPE_INVALID_64', ##< Invalid in 64 bits mode */1464 'only_64': 'DISOPTYPE_ONLY_64', ##< Only valid in 64 bits mode */1465 'default_64_op_size': 'DISOPTYPE_DEFAULT_64_OP_SIZE', ##< Default 64 bits operand size */1466 'forced_64_op_size': 'DISOPTYPE_FORCED_64_OP_SIZE', ##< Forced 64 bits operand size; regardless of prefix bytes */1467 'rexb_extends_opreg': 'DISOPTYPE_REXB_EXTENDS_OPREG', ##< REX.B extends the register field in the opcode byte */1468 'mod_fixed_11': 'DISOPTYPE_MOD_FIXED_11', ##< modrm.mod is always 11b */1469 'forced_32_op_size_x86': 'DISOPTYPE_FORCED_32_OP_SIZE_X86', ##< Forced 32 bits operand size; regardless of prefix bytes (only in 16 & 32 bits mode!) */1470 'sse': 'DISOPTYPE_SSE', ##< SSE,SSE2,SSE3,AVX,++ instruction. Not implemented yet! */1471 'mmx': 'DISOPTYPE_MMX', ##< MMX,MMXExt,3DNow,++ instruction. Not implemented yet! */1472 'fpu': 'DISOPTYPE_FPU', ##< FPU instruction. Not implemented yet! */1473 'ignores_op_size': '', ##< Ignores both operand size prefixes.1474 };1475 1476 1687 def parseTagOpHints(self, sTag, aasSections, iTagLine, iEndLine): 1477 1688 """ … … 1490 1701 fRc = True; 1491 1702 for iHint, sHint in enumerate(asHints): 1492 if sHint not in self.kdHints:1493 if sHint.strip() in self.kdHints:1703 if sHint not in g_kdHints: 1704 if sHint.strip() in g_kdHints: 1494 1705 sHint[iHint] = sHint.strip(); 1495 1706 else: … … 1525 1736 return False; 1526 1737 sDisEnum = asWords[0]; 1527 if not self.oReGroupName.match(sDisEnum): 1528 return self.errorComment(iTagLine, '%s: invalid disassembler OP_XXXX enum: %s' % (sTag, sDisEnum,)); 1738 if not self.oReDisEnum.match(sDisEnum): 1739 return self.errorComment(iTagLine, '%s: invalid disassembler OP_XXXX enum: %s (pattern: %s)' 1740 % (sTag, sDisEnum, self.oReDisEnum.pattern)); 1529 1741 1530 1742 # Set it. … … 1536 1748 return True; 1537 1749 1538 ## \@opcpuid 1539 kdCpuIdFlags = { 1540 'vme': 'X86_CPUID_FEATURE_EDX_VME', 1541 'tsc': 'X86_CPUID_FEATURE_EDX_TSC', 1542 'msr': 'X86_CPUID_FEATURE_EDX_MSR', 1543 'cx8': 'X86_CPUID_FEATURE_EDX_CX8', 1544 'sep': 'X86_CPUID_FEATURE_EDX_SEP', 1545 'cmov': 'X86_CPUID_FEATURE_EDX_CMOV', 1546 'clfsh': 'X86_CPUID_FEATURE_EDX_CLFSH', 1547 'mmx': 'X86_CPUID_FEATURE_EDX_MMX', 1548 'fxsr': 'X86_CPUID_FEATURE_EDX_FXSR', 1549 'sse': 'X86_CPUID_FEATURE_EDX_SSE', 1550 'sse2': 'X86_CPUID_FEATURE_EDX_SSE2', 1551 'sse3': 'X86_CPUID_FEATURE_ECX_SSE3', 1552 'pclmul': 'X86_CPUID_FEATURE_ECX_DTES64', 1553 'monitor': 'X86_CPUID_FEATURE_ECX_CPLDS', 1554 'vmx': 'X86_CPUID_FEATURE_ECX_VMX', 1555 'smx': 'X86_CPUID_FEATURE_ECX_TM2', 1556 'ssse3': 'X86_CPUID_FEATURE_ECX_SSSE3', 1557 'fma': 'X86_CPUID_FEATURE_ECX_FMA', 1558 'cx16': 'X86_CPUID_FEATURE_ECX_CX16', 1559 'pcid': 'X86_CPUID_FEATURE_ECX_PCID', 1560 'sse41': 'X86_CPUID_FEATURE_ECX_SSE4_1', 1561 'sse42': 'X86_CPUID_FEATURE_ECX_SSE4_2', 1562 'movbe': 'X86_CPUID_FEATURE_ECX_MOVBE', 1563 'popcnt': 'X86_CPUID_FEATURE_ECX_POPCNT', 1564 'aes': 'X86_CPUID_FEATURE_ECX_AES', 1565 'xsave': 'X86_CPUID_FEATURE_ECX_XSAVE', 1566 'avx': 'X86_CPUID_FEATURE_ECX_AVX', 1567 'f16c': 'X86_CPUID_FEATURE_ECX_F16C', 1568 'rdrand': 'X86_CPUID_FEATURE_ECX_RDRAND', 1569 1570 'axmmx': 'X86_CPUID_AMD_FEATURE_EDX_AXMMX', 1571 '3dnowext': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX', 1572 '3dnow': 'X86_CPUID_AMD_FEATURE_EDX_3DNOW', 1573 'svm': 'X86_CPUID_AMD_FEATURE_ECX_SVM', 1574 'cr8l': 'X86_CPUID_AMD_FEATURE_ECX_CR8L', 1575 'abm': 'X86_CPUID_AMD_FEATURE_ECX_ABM', 1576 'sse4a': 'X86_CPUID_AMD_FEATURE_ECX_SSE4A', 1577 '3dnowprf': 'X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF', 1578 'xop': 'X86_CPUID_AMD_FEATURE_ECX_XOP', 1579 'fma4': 'X86_CPUID_AMD_FEATURE_ECX_FMA4', 1580 }; 1750 def parseTagOpMinCpu(self, sTag, aasSections, iTagLine, iEndLine): 1751 """ 1752 Tag: \@opmincpu 1753 Value: <simple CPU name> 1754 1755 Indicates when this instruction was introduced. 1756 """ 1757 oInstr = self.ensureInstructionForOpTag(iTagLine); 1758 1759 # Flatten the value, split into words, make sure there's just one, valid it. 1760 asCpus = self.flattenAllSections(aasSections).split(); 1761 if len(asCpus) > 1: 1762 self.errorComment(iTagLine, '%s: exactly one CPU name, please: %s' % (sTag, ' '.join(asCpus),)); 1763 1764 sMinCpu = asCpus[0]; 1765 if sMinCpu in g_kdCpuNames: 1766 self.sMinCpu = sMinCpu; 1767 else: 1768 return self.errorComment(iTagLine, '%s: invalid CPU name: %s (names: %s)' 1769 % (sTag, sMinCpu, ','.join(sorted(g_kdCpuNames)),)); 1770 1771 # Set it. 1772 if oInstr.sMinCpu is None: 1773 oInstr.sMinCpu = sMinCpu; 1774 elif oInstr.sMinCpu != sMinCpu: 1775 self.errorComment(iTagLine, '%s: attemting to overwrite "%s" with "%s"' % (sTag, oInstr.sMinCpu, sMinCpu,)); 1776 1777 _ = iEndLine; 1778 return True; 1581 1779 1582 1780 def parseTagOpCpuId(self, sTag, aasSections, iTagLine, iEndLine): … … 1596 1794 fRc = True; 1597 1795 for iCpuId, sCpuId in enumerate(asCpuIds): 1598 if sCpuId not in self.kdCpuIds:1599 if sCpuId.strip() in self.kdCpuIds:1796 if sCpuId not in g_kdCpuIdFlags: 1797 if sCpuId.strip() in g_kdCpuIdFlags: 1600 1798 sCpuId[iCpuId] = sCpuId.strip(); 1601 1799 else: … … 1640 1838 return True; 1641 1839 1642 ## \@opunused, \@opinvalid, \@opinvlstyle1643 kdInvalidStyles = {1644 'immediate': [], ##< CPU stops decoding immediately after the opcode.1645 'intel-modrm': [], ##< Intel decodes ModR/M.1646 'intel-modrm-imm8': [], ##< Intel decodes ModR/M and an 8-byte immediate.1647 'intel-opcode-modrm': [], ##< Intel decodes another opcode byte followed by ModR/M. (Unused extension tables.)1648 'intel-opcode-modrm-imm8': [], ##< Intel decodes another opcode byte followed by ModR/M and an 8-byte immediate.1649 };1650 1651 1840 def parseTagOpUnusedInvalid(self, sTag, aasSections, iTagLine, iEndLine): 1652 1841 """ … … 1670 1859 return self.errorComment(iTagLine, '%s: exactly one invalid behviour style, please: %s' % (sTag, asStyles,)); 1671 1860 sStyle = asStyles[0]; 1672 if sStyle not in self.kdInvalidStyle:1861 if sStyle not in g_kdInvalidStyles: 1673 1862 return self.errorComment(iTagLine, '%s: invalid invalid behviour style: %s (valid: %s)' 1674 % (sTag, sStyle, self.kdInvalidStyles.keys(),));1863 % (sTag, sStyle, g_kdInvalidStyles.keys(),)); 1675 1864 # Set it. 1676 1865 if oInstr.sInvlStyle is not None: … … 2033 2222 return (off, asRet); 2034 2223 2035 def findAndParseMacroInvocation (self, sCode, sMacro):2224 def findAndParseMacroInvocationEx(self, sCode, sMacro): 2036 2225 """ 2037 2226 Returns (len(sCode), None) if not found, parseMacroInvocation result if found. … … 2043 2232 return (len(sCode), None); 2044 2233 2234 def findAndParseMacroInvocation(self, sCode, sMacro): 2235 """ 2236 Returns None if not found, arguments as per parseMacroInvocation if found. 2237 """ 2238 return self.findAndParseMacroInvocationEx(sCode, sMacro)[1]; 2239 2045 2240 def findAndParseFirstMacroInvocation(self, sCode, asMacro): 2046 2241 """ 2047 Returns (len(sCode), None) if not found, parseMacroInvocation result if found.2242 Returns same as findAndParseMacroInvocation. 2048 2243 """ 2049 2244 for sMacro in asMacro: 2050 offAfter,asRet = self.findAndParseMacroInvocation(sCode, sMacro);2245 asRet = self.findAndParseMacroInvocation(sCode, sMacro); 2051 2246 if asRet is not None: 2052 return (offAfter, asRet); 2053 return (len(sCode), None); 2247 return asRet; 2248 return None; 2249 2250 def workerIemOpMnemonicEx(self, sMacro, sStats, sAsm, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands): 2251 """ 2252 Processes one of the a IEMOP_MNEMONIC0EX, IEMOP_MNEMONIC1EX, IEMOP_MNEMONIC2EX, 2253 IEMOP_MNEMONIC3EX, and IEMOP_MNEMONIC4EX macros. 2254 """ 2255 # 2256 # Some invocation checks. 2257 # 2258 if sUpper != sUpper.upper(): 2259 self.error('%s: bad a_Upper parameter: %s' % (sMacro, sUpper,)); 2260 if sLower != sLower.lower(): 2261 self.error('%s: bad a_Lower parameter: %s' % (sMacro, sLower,)); 2262 if sUpper.lower() != sLower: 2263 self.error('%s: a_Upper and a_Lower parameters does not match: %s vs %s' % (sMacro, sUpper, sLower,)); 2264 if not self.oReMnemonic.match(sLower): 2265 self.error('%s: invalid a_Lower: %s (valid: %s)' % (sMacro, sLower, self.oReMnemonic.pattern,)); 2266 2267 # 2268 # Check if sIemHints tells us to not consider this macro invocation. 2269 # 2270 if sIemHints.find('IEMOPHINT_SKIP_PYTHON') >= 0: 2271 return True; 2272 2273 # Apply to the last instruction only for now. 2274 if len(self.aoCurInstrs) == 0: 2275 self.addInstruction(); 2276 oInstr = self.aoCurInstrs[-1]; 2277 if oInstr.iLineMnemonicMacro == -1: 2278 oInstr.iLineMnemonicMacro = self.iLine; 2279 else: 2280 self.error('%s: already saw a IEMOP_MNEMONIC* macro on line %u for this instruction' 2281 % (sMacro, self.iLineMnemonicMacro,)); 2282 2283 # Mnemonic 2284 if oInstr.sMnemonic is None: 2285 oInstr.sMnemonic = sLower; 2286 elif oInstr.sMnemonic != sLower: 2287 self.error('%s: current instruction and a_Lower does not match: %s vs %s' % (sMacro, oInstr.sMnemonic, sLower,)); 2288 2289 # Process operands. 2290 if len(oInstr.aoOperands) not in [0, len(asOperands)]: 2291 self.error('%s: number of operands given by @opN does not match macro: %s vs %s' 2292 % (sMacro, len(oInstr.aoOperands), len(aoOperands),)); 2293 for iOperand, sType in enumerate(asOperands): 2294 sWhere = g_kdOpTypes.get(sType, [None, None])[1]; 2295 if sWhere is None: 2296 self.error('%s: unknown a_Op%u value: %s' % (sMacro, iOperand + 1, sType)); 2297 if iOperand < len(oInstr.aoOperands): # error recovery. 2298 sWhere = oInstr.aoOperands[iOperand].sWhere; 2299 sType = oInstr.aoOperands[iOperand].sType; 2300 else: 2301 sWhere = 'reg'; 2302 sType = 'Gb'; 2303 if iOperand == len(oInstr.aoOperands): 2304 oInstr.aoOperands.append(Operand(sWhere, sType)) 2305 elif oInstr.aoOperands[iOperand].sWhere != sWhere or oInstr.aoOperands[iOperand].sType != sType: 2306 self.error('%s: @op%u and a_Op%u mismatch: %s:%s vs %s:%s' 2307 % (sMacro, iOperand + 1, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, 2308 oInstr.aoOperands[iOperand].sType, sWhere, sType,)); 2309 2310 # Encoding. 2311 if sForm not in g_kdIemForms: 2312 self.error('%s: unknown a_Form value: %s' % (sMacro, sForm,)); 2313 else: 2314 if oInstr.sEncoding is None: 2315 oInstr.sEncoding = g_kdIemForms[sForm][0]; 2316 elif g_kdIemForms[sForm][0] != oInstr.sEncoding: 2317 self.error('%s: current instruction @openc and a_Form does not match: %s vs %s (%s)' 2318 % (sMacro, oInstr.sEncoding, g_kdIemForms[sForm], sForm)); 2319 2320 # Check the parameter locations for the encoding. 2321 if g_kdIemForms[sForm][1] is not None: 2322 for iOperand, sWhere in enumerate(g_kdIemForms[sForm][1]): 2323 if oInstr.aoOperands[iOperand].sWhere != sWhere: 2324 self.error('%s: current instruction @op%u and a_Form location does not match: %s vs %s (%s)' 2325 % (sMacro, iOperand + 1, oInstr.aoOperands[iOperand].sWhere, sWhere, sForm,)); 2326 2327 # Stats. 2328 if not self.oReStatsName.match(sStats): 2329 self.error('%s: invalid a_Stats value: %s' % (sMacro, sStats,)); 2330 elif oInstr.sStats is None: 2331 oInstr.sStats = sStats; 2332 elif oInstr.sStats != sStats: 2333 self.error('%s: mismatching @opstats and a_Stats value: %s vs %s' 2334 % (sMacro, oInstr.sStats, sStats,)); 2335 2336 # Process the hints (simply merge with @ophints w/o checking anything). 2337 for sHint in sDisHints.split('|'): 2338 sHint = sHint.strip(); 2339 if sHint.startswith('DISOPTYPE_'): 2340 sShortHint = sHint[len('DISOPTYPE_'):].lower(); 2341 if sShortHint in g_kdHints: 2342 oInstr.dHints[sShortHint] = True; # (dummy value, using dictionary for speed) 2343 else: 2344 self.error('%s: unknown a_fDisHints value: %s' % (sMacro, sHint,)); 2345 elif sHint != '0': 2346 self.error('%s: expected a_fDisHints value: %s' % (sMacro, sHint,)); 2347 2348 for sHint in sIemHints.split('|'): 2349 sHint = sHint.strip(); 2350 if sHint.startswith('IEMOPHINT_'): 2351 sShortHint = sHint[len('IEMOPHINT_'):].lower(); 2352 if sShortHint in g_kdHints: 2353 oInstr.dHints[sShortHint] = True; # (dummy value, using dictionary for speed) 2354 else: 2355 self.error('%s: unknown a_fIemHints value: %s' % (sMacro, sHint,)); 2356 elif sHint != '0': 2357 self.error('%s: expected a_fIemHints value: %s' % (sMacro, sHint,)); 2358 2359 2360 return True; 2361 2362 def workerIemOpMnemonic(self, sMacro, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands): 2363 """ 2364 Processes one of the a IEMOP_MNEMONIC0, IEMOP_MNEMONIC1, IEMOP_MNEMONIC2, 2365 IEMOP_MNEMONIC3, and IEMOP_MNEMONIC4 macros. 2366 """ 2367 if asOperands == 0: 2368 return self.workerIemOpMnemonicEx(sLower, sLower, sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); 2369 return self.workerIemOpMnemonicEx(sMacro, sLower + '_' + '_'.join(asOperands), sLower + ' ' + ','.join(asOperands), 2370 sForm, sUpper, sLower, sDisHints, sIemHints, asOperands); 2054 2371 2055 2372 def checkCodeForMacro(self, sCode): … … 2062 2379 if sCode.find('(') > 0: 2063 2380 # Look for instruction decoder function definitions. ASSUME single line. 2064 (_, asArgs)= self.findAndParseFirstMacroInvocation(sCode,2065 2066 2067 2068 2069 2381 asArgs = self.findAndParseFirstMacroInvocation(sCode, 2382 [ 'FNIEMOP_DEF', 2383 'FNIEMOP_STUB', 2384 'FNIEMOP_STUB_1', 2385 'FNIEMOP_UD_STUB', 2386 'FNIEMOP_UD_STUB_1' ]); 2070 2387 if asArgs is not None: 2071 2388 sFunction = asArgs[1]; 2072 2389 2073 if len(self.asCurInstr) == 0: 2074 self.addInstruction().sMnemonic = sFunction.split('_')[1]; 2390 if len(self.aoCurInstrs) == 0: 2391 self.addInstruction(); 2392 for oInstr in self.aoCurInstrs: 2393 if oInstr.iLineFnIemOpMacro == -1: 2394 oInstr.iLineFnIemOpMacro = self.iLine; 2395 else: 2396 self.error('%s: already seen a FNIEMOP_XXX macro for %s' % (asArgs[0], oInstr,) ); 2075 2397 self.setInstrunctionAttrib('sFunction', sFunction); 2076 2398 self.setInstrunctionAttrib('fStub', asArgs[0].find('STUB') > 0, fOverwrite = True); … … 2081 2403 2082 2404 # IEMOP_MNEMONIC(a_Stats, a_szMnemonic) IEMOP_INC_STATS(a_Stats) 2083 (_, asArgs)= self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC');2405 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC'); 2084 2406 if asArgs is not None: 2085 if len(self.asCurInstr) == 1: 2086 self.setInstrunctionAttrib('sStats', asArgs[1]); 2087 self.setInstrunctionAttrib('sMnemonic', asArgs[1].split('_')[0]); 2088 2089 # IEMOP_HLP_DECODED_NL_1(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_fDisOpType) 2090 (_, asArgs) = self.findAndParseMacroInvocation(sCode, 'IEMOP_HLP_DECODED_NL_1'); 2407 if len(self.aoCurInstrs) == 1: 2408 oInstr = self.aoCurInstrs[0]; 2409 if oInstr.sStats is None: 2410 oInstr.sStats = asArgs[1]; 2411 self.deriveMnemonicAndOperandsFromStats(oInstr, asArgs[1]); 2412 2413 # IEMOP_MNEMONIC0EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) 2414 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC0EX'); 2091 2415 if asArgs is not None: 2092 if len(self.asCurInstr) == 1: 2093 self.setInstrunctionAttrib('sRawDisOpNo', asArgs[1]); 2094 self.setInstrunctionAttrib('sRawIemOpFlags', asArgs[2]); 2095 self.setInstrunctionArrayAttrib('asRawDisParams', 0, asArgs[3]); 2096 2097 # IEMOP_HLP_DECODED_NL_2(a_uDisOpNo, a_fIemOpFlags, a_uDisParam0, a_uDisParam1, a_fDisOpType) 2098 (_, asArgs) = self.findAndParseMacroInvocation(sCode, 'IEMOP_HLP_DECODED_NL_2'); 2416 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[6], asArgs[7], 2417 []); 2418 # IEMOP_MNEMONIC1EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) 2419 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC1EX'); 2099 2420 if asArgs is not None: 2100 if len(self.asCurInstr) == 1: 2101 self.setInstrunctionAttrib('sRawDisOpNo', asArgs[1]); 2102 self.setInstrunctionAttrib('sRawIemOpFlags', asArgs[2]); 2103 self.setInstrunctionArrayAttrib('asRawDisParams', 0, asArgs[3]); 2104 self.setInstrunctionArrayAttrib('asRawDisParams', 1, asArgs[4]); 2421 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[7], asArgs[8], 2422 [asArgs[6],]); 2423 # IEMOP_MNEMONIC2EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \ 2424 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2EX'); 2425 if asArgs is not None: 2426 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[8], asArgs[9], 2427 [asArgs[6], asArgs[7]]); 2428 # IEMOP_MNEMONIC3EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \ 2429 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3EX'); 2430 if asArgs is not None: 2431 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[9], 2432 asArgs[10], [asArgs[6], asArgs[7], asArgs[8],]); 2433 # IEMOP_MNEMONIC4EX(a_Stats, a_szMnemonic, a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \ 2434 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4EX'); 2435 if asArgs is not None: 2436 self.workerIemOpMnemonicEx(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], asArgs[10], 2437 asArgs[11], [asArgs[6], asArgs[7], asArgs[8], asArgs[9],]); 2438 2439 # IEMOP_MNEMONIC0(a_Form, a_Upper, a_Lower, a_fDisHints, a_fIemHints) 2440 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC0'); 2441 if asArgs is not None: 2442 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[4], asArgs[5], []); 2443 # IEMOP_MNEMONIC1(a_Form, a_Upper, a_Lower, a_Op1, a_fDisHints, a_fIemHints) 2444 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC1'); 2445 if asArgs is not None: 2446 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[5], asArgs[6], [asArgs[4],]); 2447 # IEMOP_MNEMONIC2(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_fDisHints, a_fIemHints) \ 2448 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC2'); 2449 if asArgs is not None: 2450 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[6], asArgs[7], 2451 [asArgs[4], asArgs[5],]); 2452 # IEMOP_MNEMONIC3(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_fDisHints, a_fIemHints) \ 2453 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC3'); 2454 if asArgs is not None: 2455 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[7], asArgs[8], 2456 [asArgs[4], asArgs[5], asArgs[6],]); 2457 # IEMOP_MNEMONIC4(a_Form, a_Upper, a_Lower, a_Op1, a_Op2, a_Op3, a_Op4, a_fDisHints, a_fIemHints) \ 2458 asArgs = self.findAndParseMacroInvocation(sCode, 'IEMOP_MNEMONIC4'); 2459 if asArgs is not None: 2460 self.workerIemOpMnemonic(asArgs[0], asArgs[1], asArgs[2], asArgs[3], asArgs[8], asArgs[9], 2461 [asArgs[4], asArgs[5], asArgs[6], asArgs[7],]); 2105 2462 2106 2463 return False; … … 2269 2626 for iOperand, oOperand in enumerate(oInstr.aoOperands): 2270 2627 sTmp += ' ' if iOperand == 0 else ','; 2271 sTmp += '%' + oOperand.sType;2628 sTmp += g_kdOpTypes[oOperand.sType][2]; 2272 2629 sTmp += '",'; 2273 2630 asColumns = [ sTmp, ]; … … 2277 2634 # 2278 2635 iStart = len(asColumns); 2279 if oInstr.sEncoding == 'ModR/M': 2636 if oInstr.sEncoding is None: 2637 pass; 2638 elif oInstr.sEncoding == 'ModR/M': 2280 2639 # ASSUME the first operand is using the ModR/M encoding 2281 2640 assert len(oInstr.aoOperands) >= 1 and oInstr.aoOperands[0].usesModRM(); … … 2285 2644 if len(oInstr.aoOperands) > 1 and oInstr.aoOperands[1].usesModRM(): 2286 2645 asColumns.append('IDX_UseModRM,') 2287 elif oInstr.sEncoding == 'prefix':2646 elif oInstr.sEncoding in ['prefix', 'fixed' ]: 2288 2647 pass; 2289 2648 elif oInstr.sEncoding == 'vex2': … … 2320 2679 # Check for immediates and stuff in the remaining operands. 2321 2680 for oOperand in oInstr.aoOperands[len(asColumns) - iStart:]: 2322 sIdx = Operand.kdTypes[oOperand.sType];2681 sIdx = g_kdOpTypes[oOperand.sType][0]; 2323 2682 if sIdx != 'IDX_UseModRM': 2324 2683 asColumns.append(sIdx + ','); … … 2328 2687 # Opcode and operands. 2329 2688 # 2689 assert oInstr.sDisEnum, str(oInstr); 2330 2690 asColumns.append(oInstr.sDisEnum + ','); 2331 2691 iStart = len(asColumns) … … 2339 2699 sTmp = ''; 2340 2700 for sHint in sorted(oInstr.dHints.keys()): 2341 sDefine = SimpleParser.kdHints[sHint];2701 sDefine = g_kdHints[sHint]; 2342 2702 if sDefine.startswith('DISOPTYPE_'): 2343 2703 if sTmp: … … 2380 2740 2381 2741 2742 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r65784 r65876 4771 4771 { 4772 4772 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4773 if (iReg < X86_SREG_FS) 4774 IEMOP_HLP_NO_64BIT(); 4773 Assert(iReg < X86_SREG_FS || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT); 4775 4774 IEMOP_HLP_DEFAULT_64BIT_OP_SIZE(); 4776 4775 … … 4814 4813 IEMOP_MNEMONIC(push_fs, "push fs"); 4815 4814 IEMOP_HLP_MIN_386(); 4815 IEMOP_HLP_NO_64BIT(); 4816 4816 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4817 4817 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_FS); … … 5348 5348 IEMOP_MNEMONIC(push_gs, "push gs"); 5349 5349 IEMOP_HLP_MIN_386(); 5350 IEMOP_HLP_NO_64BIT(); 5350 5351 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 5351 5352 return FNIEMOP_CALL_1(iemOpCommonPushSReg, X86_SREG_GS); -
trunk/src/VBox/VMM/include/IEMInternal.h
r65871 r65876 867 867 #define IEMOPFORM_R 3 868 868 869 /** ModR/M + VEX.vvvv: reg, vvvv, r/m */ 870 #define IEMOPFORM_RVM 4 871 872 /** ModR/M + VEX.vvvv: r/m, vvvv, reg */ 873 #define IEMOPFORM_MVR 5 874 869 875 /** Fixed register instruction, no R/M. */ 870 #define IEMOPFORM_FIXED 4876 #define IEMOPFORM_FIXED 6 871 877 872 878 /** The r/m is a register. */ … … 880 886 * @{ */ 881 887 /** Both the operand size prefixes are ignored. */ 882 #define IEMOPHINT_IGNORES_OP_SIZE RT_BIT_32(10) 888 #define IEMOPHINT_IGNORES_OP_SIZE RT_BIT_32(10) 889 /** Hint to IEMAllInstructionPython.py that this macro should be skipped. */ 890 #define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31) 883 891 /** @} */ 884 892
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