儲存庫 vbox 的更動 66751
- 時間撮記:
- 2017-5-2 下午05:12:08 (8 年 以前)
- 位置:
- trunk
- 檔案:
-
- 修改 2 筆資料
圖例:
- 未更動
- 新增
- 刪除
-
trunk/include/VBox/vmm/hm.h
r66371 r66751 157 157 VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmmcall(PVMCPU pVCpu, PCPUMCTX pCtx, bool *pfRipUpdated); 158 158 VMM_INT_DECL(VBOXSTRICTRC) HMSvmVmrun(PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPHYS GCPhysVmcb); 159 VMM_INT_DECL( int) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt);160 VMM_INT_DECL(bool) HMSvmNstGst IsInterruptPending(PCCPUMCTX pCtx);161 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, uint64_t uExitInfo1,162 uint64_t uExitInfo 2);159 VMM_INT_DECL(uint8_t) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx); 160 VMM_INT_DECL(bool) HMSvmNstGstCanTakeInterrupt(PVMCPU pVCpu, PCCPUMCTX pCtx); 161 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleCtrlIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t uExitCode, 162 uint64_t uExitInfo1, uint64_t uExitInfo2); 163 163 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleMsrIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, uint32_t idMsr, bool fWrite); 164 164 VMM_INT_DECL(VBOXSTRICTRC) HMSvmNstGstHandleIOIntercept(PVMCPU pVCpu, PCPUMCTX pCtx, PCSVMIOIOEXITINFO pIoExitInfo, -
trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp
r66700 r66751 765 765 * @retval true if there's a pending interrupt, false otherwise. 766 766 * 767 * @param pCtx The guest-CPU context. 768 */ 769 VMM_INT_DECL(bool) HMSvmNstGstIsInterruptPending(PCCPUMCTX pCtx) 767 * @param pVCpu The cross context virtual CPU structure. 768 * @param pCtx The guest-CPU context. 769 */ 770 VMM_INT_DECL(bool) HMSvmNstGstCanTakeInterrupt(PVMCPU pVCpu, PCCPUMCTX pCtx) 770 771 { 771 772 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl; 772 if (!CPUMIsGuestInNestedHwVirtMode(pCtx)) 773 return false; 773 Assert(CPUMIsGuestInNestedHwVirtMode(pCtx)); 774 774 775 775 X86RFLAGS RFlags; … … 782 782 return false; 783 783 784 return RT_BOOL(pVmcbCtrl->IntCtrl.n.u1VIrqPending); 784 if ( !pVmcbCtrl->IntCtrl.n.u1IgnoreTPR 785 && pVmcbCtrl->IntCtrl.n.u4VIntrPrio <= pVmcbCtrl->IntCtrl.n.u8VTPR) 786 return false; 787 788 /* Paranoia. */ 789 Assert(RT_BOOL(pCtx->hwvirt.svm.fGif)); 790 Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)); 791 Assert(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST)); 792 RT_NOREF(pVCpu); 793 return true; 785 794 } 786 795 … … 789 798 * Gets the pending nested-guest interrupt. 790 799 * 791 * @returns VBox status code. 792 * @retval VINF_SUCCESS on success. 793 * @retval VERR_APIC_INTR_MASKED_BY_TPR when an APIC interrupt is pending but 794 * can't be delivered due to TPR priority. 795 * @retval VERR_NO_DATA if there is no interrupt to be delivered. 796 * 800 * @returns The nested-guest interrupt to inject. 797 801 * @param pCtx The guest-CPU context. 798 * @param pu8Interrupt Where to store the interrupt. 799 */ 800 VMM_INT_DECL(int) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx, uint8_t *pu8Interrupt) 802 */ 803 VMM_INT_DECL(uint8_t) HMSvmNstGstGetInterrupt(PCCPUMCTX pCtx) 801 804 { 802 805 PCSVMVMCBCTRL pVmcbCtrl = &pCtx->hwvirt.svm.VmcbCtrl; 803 /** @todo remove later, paranoia for now. */ 804 #ifdef DEBUG_ramshankar 805 Assert(HMSvmNstGstIsInterruptPending(pCtx)); 806 #endif 807 808 *pu8Interrupt = pVmcbCtrl->IntCtrl.n.u8VIntrVector; 809 if ( pVmcbCtrl->IntCtrl.n.u1IgnoreTPR 810 || pVmcbCtrl->IntCtrl.n.u4VIntrPrio > pVmcbCtrl->IntCtrl.n.u8VTPR) 811 return VINF_SUCCESS; 812 813 return VERR_APIC_INTR_MASKED_BY_TPR; 806 return pVmcbCtrl->IntCtrl.n.u8VIntrVector; 814 807 } 815 808
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