儲存庫 vbox 的更動 66808

時間撮記:

2017-5-5 下午12:06:21 (8 年 以前)

作者:

vboxsync

訊息:

IEM: Implemented movq Vq,Wq (f3 0f 73)

位置:

trunk

檔案:

• include/VBox/disopcode.h (修改) (1 筆差異)
• src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (修改) (2 筆差異)
• src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (修改) (2 筆差異)
• src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (修改) (3 筆差異)
• src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h (修改) (3 筆差異)

trunk/include/VBox/disopcode.h

@@ -1070 +1070 @@
 #define OP_PARM_VsdZxReg        OP_PARM_Vsd             /**< Annotates that register targets get their upper bits cleared. */
 #define OP_PARM_VqHi            OP_PARM_Vdq             /**< Annotates that only YMM/XMM[127:64] are accessed. */
+#define OP_PARM_VqZxReg         OP_PARM_Vq              /**< Annotates that register targets get their upper bits cleared */
 #define OP_PARM_MbRO            OP_PARM_Mb              /**< Annotates read only memory byte operand. */
 #define OP_PARM_MdRO            OP_PARM_Md              /**< Annotates read only memory byte operand. */

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py

@@ -221 +221 @@
     'Wpd':  ( 'IDX_UseModRM',       'rm',     '%Wpd', 'Wpd',     ),
     'Wdq':  ( 'IDX_UseModRM',       'rm',     '%Wdq', 'Wdq',     ),
+    'Wq':   ( 'IDX_UseModRM',       'rm',     '%Wq',  'Wq',      ),
     'WqZxReg': ( 'IDX_UseModRM',    'rm',     '%Wq',  'Wq',      ),
 
@@ -250 +251 @@
     'Vdq':  ( 'IDX_UseModRM',       'reg',    '%Vdq', 'Vdq',     ),
     'VqHi': ( 'IDX_UseModRM',       'reg',    '%Vdq', 'VdqHi',   ),
+    'VqZxReg': ( 'IDX_UseModRM',    'reg',    '%Vq',  'VqZx',   ),
 
     # Immediate values.

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -1930 +1930 @@
  * @optest      op1=-1 op2=0x00000002dddddddd00000001eeeeeeee ->
  *              op1=0x00000002000000020000000100000001
- * @oponly
  */
 FNIEMOP_DEF(iemOp_movshdup_Vdq_Wdq)
@@ -4313 +4312 @@
 }
 
-/** Opcode 0xf3 0x0f 0x7e - movq Vq, Wq */
-FNIEMOP_STUB(iemOp_movq_Vq_Wq);
+
+/**
+ * @opcode      0x7e
+ * @opcodesub   !11 mr/reg
+ * @oppfx       0xf3
+ * @opcpuid     sse2
+ * @opgroup     og_sse2_pcksclr_datamove
+ * @opxcpttype  5
+ * @optest      op1=1 op2=2 -> op1=2
+ * @optest      op1=0 op2=-42 -> op1=-42
+ * @oponly
+ */
+FNIEMOP_DEF(iemOp_movq_Vq_Wq)
+{
+    IEMOP_MNEMONIC2(RM, MOVQ, movq, VqZxReg, Wq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT))
+    {
+        /*
+         * Register, register.
+         */
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+        IEM_MC_BEGIN(0, 2);
+        IEM_MC_LOCAL(uint64_t,                  uSrc);
+
+        IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
+
+        IEM_MC_FETCH_XREG_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB);
+        IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
+
+        IEM_MC_ADVANCE_RIP();
+        IEM_MC_END();
+    }
+    else
+    {
+        /*
+         * Memory, register.
+         */
+        IEM_MC_BEGIN(0, 2);
+        IEM_MC_LOCAL(uint64_t,                  uSrc);
+        IEM_MC_LOCAL(RTGCPTR,                   GCPtrEffSrc);
+
+        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+        IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
+
+        IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+        IEM_MC_STORE_XREG_U64_ZX_U128(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc);
+
+        IEM_MC_ADVANCE_RIP();
+        IEM_MC_END();
+    }
+    return VINF_SUCCESS;
+}
+
 /*  Opcode 0xf2 0x0f 0x7e - invalid */
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c

@@ -1767 +1767 @@
 
 
-static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd(PBS3CG1STATE pThis, unsigned iEncoding)
+static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd__OR__MODRM_VqZxReg_Wq(PBS3CG1STATE pThis,
+                                                                                                  unsigned iEncoding)
 {
     unsigned off;
@@ -2230 +2231 @@
             return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(pThis, iEncoding);
         case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
-            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd(pThis, iEncoding);
+        case BS3CG1ENC_MODRM_VqZxReg_Wq:
+            return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VsdZxReg_Wsd__OR__MODRM_VqZxReg_Wq(pThis, iEncoding);
 
         case BS3CG1ENC_MODRM_Gv_Ma:
@@ -2421 +2423 @@
 
         case BS3CG1ENC_MODRM_VsdZxReg_Wsd:
+        case BS3CG1ENC_MODRM_VqZxReg_Wq:
             pThis->iRmOp             = 1;
             pThis->iRegOp            = 0;

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h

@@ -49 +49 @@
     BS3CG1OP_Wpd,
     BS3CG1OP_Wdq,
+    BS3CG1OP_Wq,
     BS3CG1OP_WqZxReg,
 
@@ -64 +65 @@
     BS3CG1OP_Vdq,
     BS3CG1OP_VqHi,
+    BS3CG1OP_VqZxReg,
 
     BS3CG1OP_Ib,
@@ -114 +116 @@
     BS3CG1ENC_MODRM_VssZxReg_Wss,
     BS3CG1ENC_MODRM_VsdZxReg_Wsd,
+    BS3CG1ENC_MODRM_VqZxReg_Wq,
     BS3CG1ENC_MODRM_MbRO,
     BS3CG1ENC_MODRM_MdRO,