儲存庫 vbox 的更動 66932
- 時間撮記:
- 2017-5-17 上午11:02:08 (8 年 以前)
- 位置:
- trunk
- 檔案:
-
- 修改 8 筆資料
-
include/VBox/disopcode.h (修改) (2 筆差異)
-
src/VBox/VMM/VMMAll/IEMAll.cpp (修改) (2 筆差異)
-
src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py (修改) (4 筆差異)
-
src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h (修改) (1 筆差異)
-
src/VBox/VMM/include/IEMInternal.h (修改) (1 筆差異)
-
src/VBox/VMM/testcase/tstIEMCheckMc.cpp (修改) (2 筆差異)
-
src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c (修改) (9 筆差異)
-
src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h (修改) (3 筆差異)
圖例:
- 未更動
- 新增
- 刪除
-
trunk/include/VBox/disopcode.h
r66921 r66932 780 780 OP_VMOVSS, 781 781 OP_VMOVSD, 782 OP_VMOVHLPS, 783 OP_VMOVLPS, 782 784 /** @} */ 783 785 OP_END_OF_OPCODES … … 1072 1074 #define OP_PARM_HdqCss OP_PARM_Hx /**< Hdq register complements (high) a ss specifier (low). */ 1073 1075 #define OP_PARM_HdqCsd OP_PARM_Hx /**< Hdq register complements (high) a sd specifier (low). */ 1076 #define OP_PARM_HdqCq OP_PARM_Hx /**< Hdq register complements (high) a q specifier (low). */ 1074 1077 #define OP_PARM_M_RO OP_PARM_M /**< Annotates read only memory of variable operand size (xrstor). */ 1075 1078 #define OP_PARM_M_RW OP_PARM_M /**< Annotates read-write memory of variable operand size (xsave). */ -
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r66920 r66932 11601 11601 IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \ 11602 11602 } while (0) 11603 #define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \ 11604 do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \ 11605 uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 11606 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \ 11607 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \ 11608 pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0] = pXStateTmp->x87.aXMM[iYRegSrc64Tmp].au64[1]; \ 11609 pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1] = pXStateTmp->x87.aXMM[iYRegSrcHxTmp].au64[1]; \ 11610 pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \ 11611 pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \ 11612 IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \ 11613 } while (0) 11614 #define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \ 11615 do { PX86XSAVEAREA pXStateTmp = IEM_GET_CTX(pVCpu)->CTX_SUFF(pXState); \ 11616 uintptr_t const iYRegDstTmp = (a_iYRegDst); \ 11617 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \ 11618 pXStateTmp->x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \ 11619 pXStateTmp->x87.aXMM[iYRegDstTmp].au64[1] = pXStateTmp->x87.aXMM[iYRegSrcHxTmp].au64[1]; \ 11620 pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \ 11621 pXStateTmp->u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \ 11622 IEM_MC_INT_CLEAR_ZMM_256_UP(pXStateTmp, a_iYRegDst); \ 11623 } while (0) 11603 11624 11604 11625 #ifndef IEM_WITH_SETJMP … … 12649 12670 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \ 12650 12671 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) )) \ 12672 { /* likely */ } \ 12673 else \ 12674 return IEMOP_RAISE_INVALID_LOCK_PREFIX(); \ 12675 } while (0) 12676 12677 /** 12678 * Done decoding VEX instruction, raise \#UD exception if any lock, rex, repz, 12679 * repnz or size prefixes are present, or if in real or v8086 mode. 12680 */ 12681 #define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0() \ 12682 do \ 12683 { \ 12684 if (RT_LIKELY( !( pVCpu->iem.s.fPrefixes \ 12685 & (IEM_OP_PRF_LOCK | IEM_OP_PRF_REPZ | IEM_OP_PRF_REPNZ | IEM_OP_PRF_SIZE_OP | IEM_OP_PRF_REX)) \ 12686 && !IEM_IS_REAL_OR_V86_MODE(pVCpu) \ 12687 && pVCpu->iem.s.uVexLength == 0)) \ 12651 12688 { /* likely */ } \ 12652 12689 else \ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r66921 r66932 275 275 'HdqCss': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HdqCss', ), 276 276 'HdqCsd': ( 'IDX_UseModRM', 'vvvv', '%Hx', 'HdqCsd', ), 277 'HdqCq': ( 'IDX_UseModRM', 'vvvv', '%Hq', 'HdqCq', ), 277 278 278 279 # Immediate values. … … 332 333 'VEX_RM_REG': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 333 334 'VEX_RM_MEM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), 334 'VEX_XM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), # same as VEX_RM_MEM 335 'VEX_XM': ( 'VEX.ModR/M', [ 'reg', 'rm' ], ), # same as VEX_RM_MEM, typo? 335 336 'VEX_MR': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), 336 337 'VEX_MR_REG': ( 'VEX.ModR/M', [ 'rm', 'reg' ], ), … … 341 342 'VEX_R': ( 'VEX.ModR/M', [ 'reg', ], ), 342 343 'VEX_RVM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 344 'VEX_RVM_REG': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 345 'VEX_RVM_MEM': ( 'VEX.ModR/M', [ 'reg', 'vvvv', 'rm'], ), 343 346 'VEX_MVR': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 347 'VEX_MVR_REG': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 348 'VEX_MVR_MEM': ( 'VEX.ModR/M', [ 'rm', 'vvvv', 'reg'], ), 344 349 345 350 'FIXED': ( 'fixed', None, ) … … 487 492 '4UA': [], 488 493 '5': [], 494 '5LZ': [], # LZ = VEX.L must be zero. 489 495 '6': [], 490 496 '7': [], 497 '7LZ': [], 491 498 '8': [], 492 499 '11': [], -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r66921 r66932 612 612 613 613 614 FNIEMOP_STUB(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps); 615 //FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps) 616 //{ 617 // uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 618 // if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 619 // { 620 // /** 621 // * @ opcode 0x12 622 // * @ opcodesub 11 mr/reg 623 // * @ oppfx none 624 // * @ opcpuid sse 625 // * @ opgroup og_sse_simdfp_datamove 626 // * @ opxcpttype 5 627 // * @ optest op1=1 op2=2 -> op1=2 628 // * @ optest op1=0 op2=-42 -> op1=-42 629 // */ 630 // IEMOP_MNEMONIC2(RM_REG, VMOVHLPS, vmovhlps, Vq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 631 // 632 // IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 633 // IEM_MC_BEGIN(0, 1); 634 // IEM_MC_LOCAL(uint64_t, uSrc); 635 // 636 // IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 637 // IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 638 // IEM_MC_FETCH_XREG_HI_U64(uSrc, (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB); 639 // IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc); 640 // 641 // IEM_MC_ADVANCE_RIP(); 642 // IEM_MC_END(); 643 // } 644 // else 645 // { 646 // /** 647 // * @ opdone 648 // * @ opcode 0x12 649 // * @ opcodesub !11 mr/reg 650 // * @ oppfx none 651 // * @ opcpuid sse 652 // * @ opgroup og_sse_simdfp_datamove 653 // * @ opxcpttype 5 654 // * @ optest op1=1 op2=2 -> op1=2 655 // * @ optest op1=0 op2=-42 -> op1=-42 656 // * @ opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps 657 // */ 658 // IEMOP_MNEMONIC2(RM_MEM, VMOVLPS, vmovlps, Vq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 659 // 660 // IEM_MC_BEGIN(0, 2); 661 // IEM_MC_LOCAL(uint64_t, uSrc); 662 // IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 663 // 664 // IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 665 // IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 666 // IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 667 // IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE(); 668 // 669 // IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 670 // IEM_MC_STORE_XREG_U64(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, uSrc); 671 // 672 // IEM_MC_ADVANCE_RIP(); 673 // IEM_MC_END(); 674 // } 675 // return VINF_SUCCESS; 676 //} 614 FNIEMOP_DEF(iemOp_vmovlps_Vq_Hq_Mq__vmovhlps) 615 { 616 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 617 if ((bRm & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT)) 618 { 619 /** 620 * @opcode 0x12 621 * @opcodesub 11 mr/reg 622 * @oppfx none 623 * @opcpuid avx 624 * @opgroup og_avx_simdfp_datamerge 625 * @opxcpttype 7LZ 626 * @optest op2=0x22002201220222032204220522062207 627 * op3=0x3304330533063307 628 * -> op1=0x22002201220222033304330533063307 629 * @optest op2=-2 op3=-42 -> op1=-42 630 * @note op3 is only a 8-byte high XMM register half. 631 */ 632 IEMOP_MNEMONIC3(VEX_RVM, VMOVHLPS, vmovhlps, Vq_WO, HdqCq, UqHi, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 633 634 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0(); 635 IEM_MC_BEGIN(0, 0); 636 637 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 638 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 639 IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 640 (bRm & X86_MODRM_RM_MASK) | pVCpu->iem.s.uRexB, 641 pVCpu->iem.s.uVex3rdReg /*Hq*/); 642 643 IEM_MC_ADVANCE_RIP(); 644 IEM_MC_END(); 645 } 646 else 647 { 648 /** 649 * @opdone 650 * @opcode 0x12 651 * @opcodesub !11 mr/reg 652 * @oppfx none 653 * @opcpuid avx 654 * @opgroup og_avx_simdfp_datamove 655 * @opxcpttype 5LZ 656 * @opfunction iemOp_vmovlps_Vq_Hq_Mq__vmovhlps 657 * @optest op1=1 op2=0 op3=0 -> op1=0 658 * @optest op1=0 op2=-1 op3=-1 -> op1=-1 659 * @optest op1=1 op2=0x20000000000000000 op3=3 -> op1=0x20000000000000003 660 * @optest op2=-1 op3=0x42 -> op1=0xffffffffffffffff0000000000000042 661 */ 662 IEMOP_MNEMONIC3(VEX_RVM_MEM, VMOVLPS, vmovlps, Vq_WO, HdqCq, Mq, DISOPTYPE_HARMLESS, IEMOPHINT_IGNORES_OP_SIZE); 663 664 IEM_MC_BEGIN(0, 2); 665 IEM_MC_LOCAL(uint64_t, uSrc); 666 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 667 668 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 669 IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0(); 670 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 671 IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE(); 672 673 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 674 IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(((bRm >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) | pVCpu->iem.s.uRexReg, 675 uSrc, 676 pVCpu->iem.s.uVex3rdReg /*Hq*/); 677 678 IEM_MC_ADVANCE_RIP(); 679 IEM_MC_END(); 680 } 681 return VINF_SUCCESS; 682 } 677 683 678 684 -
trunk/src/VBox/VMM/include/IEMInternal.h
r66901 r66932 910 910 #define IEMOPFORM_VEX_RM 4 911 911 /** VEX+ModR/M: reg, r/m (register) */ 912 #define IEMOPFORM_VEX_RM_REG 912 #define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM | IEMOPFORM_MOD3) 913 913 /** VEX+ModR/M: reg, r/m (memory) */ 914 #define IEMOPFORM_VEX_RM_MEM 915 #define IEMOPFORM_VEX_XM 914 #define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM | IEMOPFORM_NOT_MOD3) 915 #define IEMOPFORM_VEX_XM IEMOPFORM_VEX_RM_MEM 916 916 /** VEX+ModR/M: r/m, reg */ 917 917 #define IEMOPFORM_VEX_MR 5 918 918 /** VEX+ModR/M: r/m (register), reg */ 919 #define IEMOPFORM_VEX_MR_REG 919 #define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR | IEMOPFORM_MOD3) 920 920 /** VEX+ModR/M: r/m (memory), reg */ 921 #define IEMOPFORM_VEX_MR_MEM 921 #define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR | IEMOPFORM_NOT_MOD3) 922 922 /** VEX+ModR/M: r/m only */ 923 923 #define IEMOPFORM_VEX_M 6 924 924 /** VEX+ModR/M: r/m only (register). */ 925 #define IEMOPFORM_VEX_M_REG 925 #define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M | IEMOPFORM_MOD3) 926 926 /** VEX+ModR/M: r/m only (memory). */ 927 #define IEMOPFORM_VEX_M_MEM 927 #define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M | IEMOPFORM_NOT_MOD3) 928 928 /** VEX+ModR/M: reg only */ 929 929 #define IEMOPFORM_VEX_R 7 930 930 /** VEX+ModR/M: reg, vvvv, r/m */ 931 931 #define IEMOPFORM_VEX_RVM 8 932 /** VEX+ModR/M: reg, vvvv, r/m (register). */ 933 #define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM | IEMOPFORM_MOD3) 934 /** VEX+ModR/M: reg, vvvv, r/m (memory). */ 935 #define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM | IEMOPFORM_NOT_MOD3) 932 936 /** VEX+ModR/M: r/m, vvvv, reg */ 933 937 #define IEMOPFORM_VEX_MVR 9 938 /** VEX+ModR/M: r/m, vvvv, reg (register) */ 939 #define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR | IEMOPFORM_MOD3) 940 /** VEX+ModR/M: r/m, vvvv, reg (memory) */ 941 #define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR | IEMOPFORM_NOT_MOD3) 934 942 935 943 /** Fixed register instruction, no R/M. */ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r66909 r66932 122 122 #define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0) 123 123 #define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX() do { } while (0) 124 #define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_L0() do { } while (0) 124 125 #define IEMOP_HLP_DONE_DECODING_NO_AVX_PREFIX_AND_NO_VVVV() do { } while (0) 125 126 #define IEMOP_HLP_DONE_DECODING_NO_LOCK_REPZ_OR_REPNZ_PREFIXES() do { } while (0) … … 532 533 #define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; } while (0) 533 534 #define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) do { (void)fAvxWrite; } while (0) 534 #define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 535 #define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 535 #define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 536 #define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 537 #define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 538 #define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) do { (void)fAvxWrite; } while (0) 536 539 537 540 #define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0) -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c
r66921 r66932 2426 2426 2427 2427 2428 /** 2429 * Wip - VEX.W ignored. 2430 * Lig - VEX.L ignored. 2431 */ 2428 2432 static unsigned BS3_NEAR_CODE 2429 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_ OR_Vice_Versa(PBS3CG1STATE pThis, unsigned iEncoding)2433 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 2430 2434 { 2431 2435 unsigned off; … … 2477 2481 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 0; 2478 2482 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2483 break; 2484 case 5: 2485 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/); 2486 off = Bs3Cg1InsertOpcodes(pThis, off); 2487 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2488 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2489 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 3; 2490 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2491 break; 2492 case 6: 2493 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/); 2494 off = Bs3Cg1InsertOpcodes(pThis, off); 2495 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2496 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2497 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7); 2498 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2499 break; 2500 case 7: 2501 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2502 off = Bs3Cg1InsertOpcodes(pThis, off); 2503 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2504 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2505 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7); 2506 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2507 break; 2508 default: 2509 return 0; 2510 } 2511 pThis->cbCurInstr = off; 2512 return iEncoding + 1; 2513 } 2514 2515 2516 /** 2517 * Wip - VEX.W ignored. 2518 */ 2519 static unsigned BS3_NEAR_CODE 2520 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 2521 { 2522 unsigned off; 2523 switch (iEncoding) 2524 { 2525 case 0: 2526 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/); 2527 off = Bs3Cg1InsertOpcodes(pThis, off); 2528 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2529 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2530 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 0; 2531 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2532 break; 2533 case 1: 2534 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x8 /*~V*/, 1 /*L-ignored*/, 1 /*~R*/); 2535 off = Bs3Cg1InsertOpcodes(pThis, off); 2536 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 3, 1); 2537 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 3; 2538 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 7; 2539 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2540 pThis->fInvalidEncoding = true; 2541 break; 2542 case 2: 2543 #if ARCH_BITS == 64 2544 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode)) 2545 { 2546 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 0 /*L*/, 0 /*~R*/); 2547 off = Bs3Cg1InsertOpcodes(pThis, off); 2548 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 3, 2); 2549 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 11; 2550 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 15; 2551 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 2; 2552 break; 2553 } 2554 #endif 2555 /* fall thru */ 2556 case 3: 2557 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2558 off = Bs3Cg1InsertOpcodes(pThis, off); 2559 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2560 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2561 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 0; 2562 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2563 break; 2564 case 4: 2565 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L - ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2566 off = Bs3Cg1InsertOpcodes(pThis, off); 2567 pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 1); 2568 pThis->aOperands[pThis->iRegOp].idxField = pThis->aOperands[pThis->iRegOp].idxFieldBase + 2; 2569 pThis->aOperands[1 ].idxField = pThis->aOperands[1 ].idxFieldBase + 0; 2570 pThis->aOperands[pThis->iRmOp ].idxField = pThis->aOperands[pThis->iRmOp ].idxFieldBase + 1; 2571 pThis->fInvalidEncoding = true; 2479 2572 break; 2480 2573 case 5: … … 2611 2704 2612 2705 2706 /** 2707 * Wip - VEX.W ignored. 2708 */ 2709 static unsigned BS3_NEAR_CODE 2710 Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa(PBS3CG1STATE pThis, unsigned iEncoding) 2711 { 2712 unsigned off; 2713 switch (iEncoding) 2714 { 2715 case 0: 2716 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xc /*~V*/, 0 /*L*/, 1 /*~R*/); 2717 off = Bs3Cg1InsertOpcodes(pThis, off); 2718 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 2719 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 3; 2720 break; 2721 case 1: 2722 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L*/, 1 /*~R*/); 2723 off = Bs3Cg1InsertOpcodes(pThis, off); 2724 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7, 0); 2725 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2726 pThis->fInvalidEncoding = true; 2727 break; 2728 case 2: 2729 #if ARCH_BITS == 64 2730 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode)) 2731 { 2732 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0x1 /*~V*/, 0 /*L*/, 0 /*~R*/); 2733 off = Bs3Cg1InsertOpcodes(pThis, off); 2734 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 7 + 8, 0); 2735 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 14; 2736 break; 2737 } 2738 #endif 2739 /* fall thru */ 2740 case 3: 2741 iEncoding = 3; 2742 off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /*offDst*/, 0xe /*~V*/, 0 /*L*/, 1 /*~R*/); 2743 off = Bs3Cg1InsertOpcodes(pThis, off); 2744 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 0, 0); 2745 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 1; 2746 break; 2747 case 4: 2748 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2749 off = Bs3Cg1InsertOpcodes(pThis, off); 2750 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 2751 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2752 break; 2753 case 5: 2754 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 1 /*L-ignored*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2755 off = Bs3Cg1InsertOpcodes(pThis, off); 2756 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 2757 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2758 pThis->fInvalidEncoding = true; 2759 break; 2760 case 6: 2761 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 1 /*W-ignored*/); 2762 off = Bs3Cg1InsertOpcodes(pThis, off); 2763 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 2764 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2765 break; 2766 case 7: 2767 #if ARCH_BITS == 64 2768 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode)) 2769 { 2770 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 0 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2771 off = Bs3Cg1InsertOpcodes(pThis, off); 2772 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5+8, 0); 2773 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2774 break; 2775 } 2776 #endif 2777 /* fall thru */ 2778 case 8: 2779 #if ARCH_BITS == 64 2780 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode)) 2781 { 2782 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 1 /*~X*/, 0 /*~B-ignored*/, 0 /*W*/); 2783 off = Bs3Cg1InsertOpcodes(pThis, off); 2784 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 1, 0); 2785 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2786 break; 2787 } 2788 #endif 2789 /* fall thru */ 2790 case 9: 2791 #if ARCH_BITS == 64 2792 if (BS3_MODE_IS_64BIT_CODE(pThis->bMode)) 2793 { 2794 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0xf /*~V*/, 0 /*L*/, 1 /*~R*/, 0 /*~X-ignored*/, 1 /*~B*/, 0 /*W*/); 2795 off = Bs3Cg1InsertOpcodes(pThis, off); 2796 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 2, 0); 2797 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + 0; 2798 break; 2799 } 2800 #endif 2801 /* fall thru */ 2802 case 10: 2803 iEncoding = 10; 2804 off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /*offDst*/, 0 /*~V*/, 1 /*L*/, 1 /*~R*/, 1 /*~X*/, 1 /*~B*/, 0 /*W*/); 2805 off = Bs3Cg1InsertOpcodes(pThis, off); 2806 off = Bs3Cfg1EncodeMemMod0DispWithRegFieldAndDefaults(pThis, false, off, 5, 0); 2807 pThis->aOperands[1].idxField = pThis->aOperands[1].idxFieldBase + (BS3_MODE_IS_64BIT_CODE(pThis->bMode) ? 15 : 7); 2808 pThis->fInvalidEncoding = true; 2809 break; 2810 default: 2811 return 0; 2812 } 2813 pThis->cbCurInstr = off; 2814 return iEncoding + 1; 2815 } 2816 2817 2613 2818 static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_VEX_MODRM_Md_WO(PBS3CG1STATE pThis, unsigned iEncoding) 2614 2819 { … … 3294 3499 3295 3500 case BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss: 3296 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_ OR_Vice_Versa;3501 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa; 3297 3502 pThis->iRegOp = 0; 3298 3503 pThis->iRmOp = 2; … … 3321 3526 3322 3527 case BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd: 3323 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_ OR_Vice_Versa;3528 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa; 3324 3529 pThis->iRegOp = 0; 3325 3530 pThis->iRmOp = 2; … … 3335 3540 break; 3336 3541 3542 case BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi: 3543 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Wip_OR_ViceVersa; 3544 pThis->iRegOp = 0; 3545 pThis->iRmOp = 2; 3546 pThis->aOperands[0].cbOp = 16; 3547 pThis->aOperands[1].cbOp = 16; 3548 pThis->aOperands[2].cbOp = 8; 3549 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 3550 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; 3551 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_CTX; 3552 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0; 3553 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0; 3554 pThis->aOperands[2].idxFieldBase = BS3CG1DST_XMM0_HI; 3555 break; 3556 3557 case BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq: 3558 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Hsomething_Msomething_Wip_OR_ViceVersa; 3559 pThis->iRegOp = 0; 3560 pThis->iRmOp = 2; 3561 pThis->aOperands[0].cbOp = 16; 3562 pThis->aOperands[1].cbOp = 16; 3563 pThis->aOperands[2].cbOp = 8; 3564 pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX_ZX_VLMAX; 3565 pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX; 3566 pThis->aOperands[2].enmLocation = BS3CG1OPLOC_MEM; 3567 pThis->aOperands[0].idxFieldBase = BS3CG1DST_XMM0; 3568 pThis->aOperands[1].idxFieldBase = BS3CG1DST_XMM0; 3569 pThis->aOperands[2].idxFieldBase = BS3CG1DST_INVALID; 3570 break; 3571 3337 3572 case BS3CG1ENC_VEX_MODRM_Md_WO_Vss: 3338 3573 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_Msomething_Wip_Lig_OR_ViceVersa; … … 3360 3595 3361 3596 case BS3CG1ENC_VEX_MODRM_Uss_WO_HdqCss_Vss: 3362 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_ OR_Vice_Versa;3597 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa; 3363 3598 pThis->iRegOp = 2; 3364 3599 pThis->iRmOp = 0; … … 3375 3610 3376 3611 case BS3CG1ENC_VEX_MODRM_Usd_WO_HdqCsd_Vsd: 3377 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_ OR_Vice_Versa;3612 pThis->pfnEncoder = Bs3Cg1EncodeNext_VEX_MODRM_VsomethingWO_HdqCsomething_Usomething_Lip_Wip_OR_ViceVersa; 3378 3613 pThis->iRegOp = 2; 3379 3614 pThis->iRmOp = 0; … … 5025 5260 #if 0 5026 5261 /* (for debugging) */ 5027 if (bMode == BS3_MODE_RM)5262 if (bMode != BS3_MODE_PP32) 5028 5263 return BS3TESTDOMODE_SKIPPED; 5029 5264 #endif -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1.h
r66921 r66932 63 63 BS3CG1OP_HdqCss, 64 64 BS3CG1OP_HdqCsd, 65 BS3CG1OP_HdqCq, 65 66 BS3CG1OP_Nq, 66 67 BS3CG1OP_Pq_WO, … … 152 153 BS3CG1ENC_VEX_MODRM_Vss_WO_HdqCss_Uss, 153 154 BS3CG1ENC_VEX_MODRM_Vsd_WO_HdqCsd_Usd, 155 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_UqHi, 156 BS3CG1ENC_VEX_MODRM_Vq_WO_HdqCq_Mq, 154 157 BS3CG1ENC_VEX_MODRM_VssZx_WO_Md, 155 158 BS3CG1ENC_VEX_MODRM_VsdZx_WO_Mq, … … 230 233 BS3CG1XCPTTYPE_4UA, 231 234 BS3CG1XCPTTYPE_5, 235 BS3CG1XCPTTYPE_5LZ, 232 236 BS3CG1XCPTTYPE_6, 233 237 BS3CG1XCPTTYPE_7, 238 BS3CG1XCPTTYPE_7LZ, 234 239 BS3CG1XCPTTYPE_8, 235 240 BS3CG1XCPTTYPE_11,
注意:
瀏覽 TracChangeset
來幫助您使用更動檢視器
