vbox的更動 98914 路徑 trunk/src/VBox/Additions/3D

時間撮記:

2023-3-11 下午11:08:00 (21 月 以前)

作者:

vboxsync

訊息:

Additions/3D/mesa: TGSI_OPCODE_ARR and fix for indirect addressing in the TGSI->VGPU10 shader translation code

檔案:

• trunk/src/VBox/Additions/3D/mesa/mesa-21.3.8/src/gallium/drivers/svga/svga_tgsi_vgpu10.c (修改) (7 筆差異)

trunk/src/VBox/Additions/3D/mesa/mesa-21.3.8/src/gallium/drivers/svga/svga_tgsi_vgpu10.c

@@ -1156 +1156 @@
 static void
 emit_indirect_register(struct svga_shader_emitter_v10 *emit,
+#ifndef VBOX_WITH_MESA3D_NINE_SVGA
                        unsigned addr_reg_index)
+#else
+                       unsigned addr_reg_index,
+                       unsigned addr_reg_select)
+#endif
 {
    unsigned tmp_reg_index;
@@ -1172 +1177 @@
    operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
    operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
+#ifndef VBOX_WITH_MESA3D_NINE_SVGA
    operand0.swizzleX = 0;
    operand0.swizzleY = 1;
    operand0.swizzleZ = 2;
    operand0.swizzleW = 3;
+#else
+   operand0.selectMask = addr_reg_select;
+#endif
 
    emit_dword(emit, operand0.value);
@@ -1436 +1445 @@
 
    if (indirect) {
+#ifndef VBOX_WITH_MESA3D_NINE_SVGA
       emit_indirect_register(emit, reg->Indirect.Index);
+#else
+      emit_indirect_register(emit, reg->Indirect.Index, reg->Indirect.Swizzle);
+#endif
    }
 }
@@ -1828 +1841 @@
 
          if (indirect2d) {
+#ifndef VBOX_WITH_MESA3D_NINE_SVGA
             emit_indirect_register(emit, reg->DimIndirect.Index);
+#else
+            emit_indirect_register(emit, reg->DimIndirect.Index, reg->DimIndirect.Swizzle);
+#endif
          }
       }
@@ -1835 +1852 @@
 
       if (indirect) {
+#ifndef VBOX_WITH_MESA3D_NINE_SVGA
          emit_indirect_register(emit, reg->Indirect.Index);
+#else
+         emit_indirect_register(emit, reg->Indirect.Index, reg->Indirect.Swizzle);
+#endif
       }
    }
@@ -6402 +6423 @@
 }
 
+
+#ifdef VBOX_WITH_MESA3D_NINE_SVGA
+/**
+ * Emit code for TGSI_OPCODE_ARR instruction.
+ */
+static boolean
+emit_arr(struct svga_shader_emitter_v10 *emit,
+         const struct tgsi_full_instruction *inst)
+{
+   unsigned index = inst->Dst[0].Register.Index;
+   struct tgsi_full_src_register half = make_immediate_reg_float(emit, 0.5f);
+   struct tgsi_full_dst_register address_reg_dst;
+   struct tgsi_full_src_register address_reg_src;
+   VGPU10_OPCODE_TYPE opcode;
+
+   assert(index < MAX_VGPU10_ADDR_REGS);
+   address_reg_dst = make_dst_temp_reg(emit->address_reg_index[index]);
+   address_reg_dst = writemask_dst(&address_reg_dst, inst->Dst[0].Register.WriteMask);
+
+   address_reg_src = make_src_temp_reg(emit->address_reg_index[index]);
+
+   /* ARR dst, s0
+    * Translates into:
+    * ADD address_tmp, s0, 0.5f
+    * FTOI address_tmp, address_tmp
+    */
+
+   emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &address_reg_dst, &inst->Src[0], &half);
+   emit_instruction_op1(emit, VGPU10_OPCODE_FTOI, &address_reg_dst, &address_reg_src);
+
+   return TRUE;
+}
+#endif
 
 /**
@@ -9380 +9434 @@
    case TGSI_OPCODE_UARL:
       return emit_arl_uarl(emit, inst);
+#ifdef VBOX_WITH_MESA3D_NINE_SVGA
+   case TGSI_OPCODE_ARR:
+      return emit_arr(emit, inst);
+#endif
    case TGSI_OPCODE_BGNSUB:
       /* no-op */