; $Id: bs3-cpu-instr-2-template.mac 70651 2018-01-19 16:00:42Z vboxsync $
;; @file
; BS3Kit - bs3-cpu-instr-2 assembly template.
;

;
; Copyright (C) 2007-2017 Oracle Corporation
;
; This file is part of VirtualBox Open Source Edition (OSE), as
; available from http://www.virtualbox.org. This file is free software;
; you can redistribute it and/or modify it under the terms of the GNU
; General Public License (GPL) as published by the Free Software
; Foundation, in version 2 as it comes in the "COPYING" file of the
; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
;
; The contents of this file may alternatively be used under the terms
; of the Common Development and Distribution License Version 1.0
; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
; VirtualBox OSE distribution, in which case the provisions of the
; CDDL are applicable instead of those of the GPL.
;
; You may elect to license modified versions of this file under the
; terms and conditions of either the GPL or the CDDL or both.
;


;*********************************************************************************************************************************
;*  Header Files                                                                                                                 *
;*********************************************************************************************************************************
%include "bs3kit-template-header.mac"   ; setup environment


;*********************************************************************************************************************************
;*  External Symbols                                                                                                             *
;*********************************************************************************************************************************
TMPL_BEGIN_TEXT


;
; Test code snippets containing code which differs between 16-bit, 32-bit
; and 64-bit CPUs modes.
;
%ifdef BS3_INSTANTIATING_CMN

BS3_PROC_BEGIN_CMN bs3CpuInstr2_mul_xBX_ud2, BS3_PBC_NEAR
        mul     xBX
.again:
        ud2
        jmp     .again
BS3_PROC_END_CMN   bs3CpuInstr2_mul_xBX_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xBX_ud2, BS3_PBC_NEAR
        imul    xBX
.again:
        ud2
        jmp     .again
BS3_PROC_END_CMN   bs3CpuInstr2_imul_xBX_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_imul_xCX_xBX_ud2, BS3_PBC_NEAR
        imul    xCX, xBX
.again:
        ud2
        jmp     .again
BS3_PROC_END_CMN   bs3CpuInstr2_imul_xCX_xBX_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_div_xBX_ud2, BS3_PBC_NEAR
        div     xBX
.again:
        ud2
        jmp     .again
BS3_PROC_END_CMN   bs3CpuInstr2_div_xBX_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_idiv_xBX_ud2, BS3_PBC_NEAR
        idiv    xBX
.again:
        ud2
        jmp     .again
BS3_PROC_END_CMN   bs3CpuInstr2_idiv_xBX_ud2


 %if TMPL_BITS == 64
BS3_PROC_BEGIN_CMN bs3CpuInstr2_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 4)
BS3_PROC_END_CMN   bs3CpuInstr2_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        lock cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_lock_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        o16 cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_o16_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        db 0f0h, 066h
        cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 6)
BS3_PROC_END_CMN   bs3CpuInstr2_lock_o16_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        repz cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_repz_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        db 0f0h, 0f3h
        cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 6)
BS3_PROC_END_CMN   bs3CpuInstr2_lock_repz_cmpxchg16b_rdi_ud2

BS3_PROC_BEGIN_CMN bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        repnz cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_repnz_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2, BS3_PBC_NEAR
        db 0f0h, 0f2h
        cmpxchg16b [rdi]
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 6)
BS3_PROC_END_CMN   bs3CpuInstr2_lock_repnz_cmpxchg16b_rdi_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_ud2, BS3_PBC_NEAR
        wrfsbase rbx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_wrfsbase_rbx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_ud2, BS3_PBC_NEAR
        wrfsbase ebx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 4)
BS3_PROC_END_CMN   bs3CpuInstr2_wrfsbase_ebx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_ud2, BS3_PBC_NEAR
        wrgsbase rbx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_wrgsbase_rbx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_ud2, BS3_PBC_NEAR
        wrgsbase ebx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 4)
BS3_PROC_END_CMN   bs3CpuInstr2_wrgsbase_ebx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2, BS3_PBC_NEAR
        wrfsbase rbx
        rdfsbase rcx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 10)
BS3_PROC_END_CMN   bs3CpuInstr2_wrfsbase_rbx_rdfsbase_rcx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2, BS3_PBC_NEAR
        wrfsbase ebx
        rdfsbase ecx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 8)
BS3_PROC_END_CMN   bs3CpuInstr2_wrfsbase_ebx_rdfsbase_ecx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2, BS3_PBC_NEAR
        wrgsbase rbx
        rdgsbase rcx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 10)
BS3_PROC_END_CMN   bs3CpuInstr2_wrgsbase_rbx_rdgsbase_rcx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_wrgsbase_ebx_rdgsbase_ecx_ud2, BS3_PBC_NEAR
        wrgsbase ebx
        rdgsbase ecx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 8)
BS3_PROC_END_CMN   bs3CpuInstr2_wrfgbase_ebx_rdgsbase_ecx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_rbx_ud2, BS3_PBC_NEAR
        rdfsbase rbx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_rdfsbase_rbx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdfsbase_ebx_ud2, BS3_PBC_NEAR
        rdfsbase ebx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 4)
BS3_PROC_END_CMN   bs3CpuInstr2_rdfsbase_ebx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_rbx_ud2, BS3_PBC_NEAR
        rdgsbase rbx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 5)
BS3_PROC_END_CMN   bs3CpuInstr2_rdgsbase_rbx_ud2


BS3_PROC_BEGIN_CMN bs3CpuInstr2_rdgsbase_ebx_ud2, BS3_PBC_NEAR
        rdgsbase ebx
.again:
        ud2
        jmp     .again
AssertCompile(.again - BS3_LAST_LABEL == 4)
BS3_PROC_END_CMN   bs3CpuInstr2_rdgsbase_ebx_ud2


;; @todo figure out this fudge. sigh.
times (348) db 0cch ; fudge to avoid 'rderr' during boot.

 %endif ; TMPL_BITS == 64


%endif ; BS3_INSTANTIATING_CMN

%include "bs3kit-template-footer.mac"   ; reset environment