; $Id: bs3-cpu-instr-3-template.mac 95401 2022-06-27 20:54:00Z vboxsync $ ;; @file ; BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, assembly template. ; ; ; Copyright (C) 2007-2022 Oracle Corporation ; ; This file is part of VirtualBox Open Source Edition (OSE), as ; available from http://www.virtualbox.org. This file is free software; ; you can redistribute it and/or modify it under the terms of the GNU ; General Public License (GPL) as published by the Free Software ; Foundation, in version 2 as it comes in the "COPYING" file of the ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. ; ; The contents of this file may alternatively be used under the terms ; of the Common Development and Distribution License Version 1.0 ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the ; VirtualBox OSE distribution, in which case the provisions of the ; CDDL are applicable instead of those of the GPL. ; ; You may elect to license modified versions of this file under the ; terms and conditions of either the GPL or the CDDL or both. ; ;********************************************************************************************************************************* ;* Header Files * ;********************************************************************************************************************************* %include "bs3kit-template-header.mac" ; setup environment ;********************************************************************************************************************************* ;* External Symbols * ;********************************************************************************************************************************* TMPL_BEGIN_TEXT ; ; Test code snippets containing code which differs between 16-bit, 32-bit ; and 64-bit CPUs modes. ; %ifdef BS3_INSTANTIATING_CMN ;; ; Variant on BS3_PROC_BEGIN_CMN w/ BS3_PBC_NEAR that prefixes the function ; with an instruction length byte. ; ; ASSUMES the length is between the start of the function and the .again label. ; %ifndef BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED %define BS3CPUINSTR3_PROC_BEGIN_CMN_DEFINED %macro BS3CPUINSTR3_PROC_BEGIN_CMN 1 align 8, db 0cch db BS3_CMN_NM(%1).again - BS3_CMN_NM(%1) BS3_PROC_BEGIN_CMN %1, BS3_PBC_NEAR %endmacro %endif ; ; PXOR (SSE2) & VPXOR (AVX2) ; BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_pxor_MM1_MM2_icebp pxor mm1, mm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_pxor_MM1_MM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_pxor_MM1_FSxBX_icebp pxor mm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_pxor_MM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_pxor_XMM1_XMM2_icebp pxor xmm1, xmm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_pxor_XMM1_XMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_pxor_XMM1_FSxBX_icebp pxor xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_pxor_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp vpxor xmm1, xmm1, xmm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp vpxor xmm1, xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp vpxor ymm7, ymm2, ymm3 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp vpxor ymm7, ymm2, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp ; ; XORPS (SSE2) & VXORPS (AVX) ; BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_xorps_XMM1_XMM2_icebp xorps xmm1, xmm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_xorps_XMM1_XMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_xorps_XMM1_FSxBX_icebp xorps xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_xorps_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp vxorps xmm1, xmm1, xmm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp vxorps xmm1, xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp vxorps ymm1, ymm1, ymm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp vxorps ymm1, ymm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp ; ; XORPD (SSE2) & VXORPD (AVX) ; BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_xorpd_XMM1_XMM2_icebp xorpd xmm1, xmm2 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_xorpd_XMM1_XMM2_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp xorpd xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp vxorpd xmm2, xmm1, xmm0 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp vxorpd xmm2, xmm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp vxorpd ymm2, ymm1, ymm0 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp vxorpd ymm2, ymm1, [fs:xBX] .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp %if TMPL_BITS == 64 BS3CPUINSTR3_PROC_BEGIN_CMN bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp vxorpd ymm10, ymm8, ymm15 .again: icebp jmp .again BS3_PROC_END_CMN bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp %endif %endif ; BS3_INSTANTIATING_CMN %include "bs3kit-template-footer.mac" ; reset environment